Method for locking and unlocking a computer address

Claim 2

In a first computer processor connected through a bus to a memory resource, a second processor, and an address control means for controlling access to addresses accessed through the bus, said first computer processor executing a program task defined by a series of microinstructions including a lock instruction and an unlock instruction, a method for locking a memory address accessible through the bus and for unlocking the memory address, comprising the steps of: (a) supplying the lock instruction from the program to the first computer processor; (b) executing the lock instruction in the first computer processor, including assigning a first value to a lock flag in a register in the first computer processor, but not actually locking an address; (c) supplying the next instruction from the program to the first computer processor; (d) if said next instruction in step (c) does not request a memory access, then executing said next instruction and repeating said step (c) to supply a next following instruction; (e) if said next instruction in step (c) does request a memory access to a requested address, then executing said next instruction, locking the requested address by asserting a lock signal from the first computer processor to the address control means such that the requested address can be accessed only by said first computer processor, and then repeating said step (c) to supply a next following instruction; (f) if a next instruction in said step (c) is an unlock instruction subsequent to locking a requested address in said step (e), then executing said unlock instruction, including assigning a second value to the lock flag so that the requested address is unlocked by asserting the lock signal upon the next following instruction supplied from the program that requests a memory access.

Claim 3

The method of claim 1 for locking and unlocking a computer address, wherein: in said step (b), executing the lock instruction includes disabling external interrupts generated from sources external to the program; and said step (f) includes enabling said external interrupts upon executing said unlock instruction.

Claim 4

The method of claim 1 for locking and unlocking a computer address, wherein the first value is a logical one and the second value is a logical zero.

Claim 5

The method of claim 1, wherein if a trap condition occurs following said step (b) but before unlocking the address, then the method further comprises the steps of: (g) assigning a second value to the lock flag to indicate that locking is not requested; (h) storing in a fault instruction register an address of the instruction that caused the trap condition; (i) executing a trap handler routine that reads the address of the instruction that caused the trap condition and handles the trap condition; (j) scanning backward through the series of microinstructions to the lock instruction previously executed in said step (b); and (k) repeated said steps (b) through (f).

Claim 6

The method of claim 4 for locking and unlocking a computer address wherein: in said step (b), executing the lock instruction includes disabling external interrupts; said step (f) includes enabling said external interrupts; and said step (g) includes enabling said external interrupts.

Claim 7

The method of claim 4 for locking a computer address, wherein the first value is a logical one.

Claim 8

The method of claim 1 for locking and unlocking a computer address, further comprising a step (g) of: (g) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a memory access has not been requested in step (e) so that no address has been locked, and if an unlock instruction has not been executed in the step (g), then a second value is assigned to the lock flag indicating that locking is no longer requested.

Claim 9

The method of claim 7, wherein N is in an approximate range between twenty-five and thirty-five.

Claim 10

The method of claim 1, further comprising a step (g) of: (g) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a requested address has been locked in step (e) without unlocking in said step (f), then unlocking the requested address.

Claim 11

The method of claim 9, wherein N is in an approximate range between twenty-five and thirty-five.

Claim 12

The method of claim 1, wherein said step (f) includes the sub-steps of: (f)(1) assigning a second value to the lock flag to indicate that unlocking has been requested; (f)(2) supplying and executing a next instruction in the series of instructions; (f)(3) if said next instruction does not request a memory access, then repeating said step (f)(2) to supply and execute a next following instruction; (f)(4) if said next instruction requests a memory access, then unlocking the requested address locked in the step (e) so that said address can be accessed by another task.

Claim 13

The method of claim 11 for locking and unlocking a computer address, wherein: in said step (b), executing the lock instruction includes disabling external interrupts generated from a source external to the program; and said step (f) includes a sub-step (f)(5) of enabling said external interrupts.

Claim 14

In a first computer processor connected through a bus to an external memory, a second processor, and an address locking means for locking an address, a method for executing a program including a series of instructions, said instructions including an interlocked operation defined by instructions between a lock instruction and an unlock instruction, said interlocked instructions including an instruction that accesses the external memory, said method comprising the steps of: (a) supplying the lock instruction from the program to the first computer processor; (b) executing the lock instruction in the first computer processor, including assigning a first value to a lock flag in the first computer processor and disabling external interrupts generated from sources external to the program, but not locking an address; (c) supplying the next instruction in the interlocked series of instructions to the first computer processor; (d) if in said step (c) said next instruction does not request a memory access and is not an unlock instruction, then executing said next instruction and repeating said step (c) to supply a next following instruction; (e) if in said step (c) said next instruction does request a memory access to a requested address, then asserting a lock signal from said first computer processor for locking the requested address such that the requested address can be accessed only by the task that requested the memory access, and then repeating said step (c) to supply a next following instruction; (f) if in said step (c) said next instruction is an unlock instruction, the executing said unlock instruction, including assigning a second value to the lock flag to indicate that unlocking has been requested, but not actually unlocking said requested address; and (g) following execution of the unlock instruction in the step (f), supplying a next instruction to the first computer processor, and if said next instruction requests a memory access, then enabling said external interrupts and de-asserting the lock signal to unlock the requested address.

Claim 15

In a first computer processor connected through a bus to an external memory, a second processor, and an address locking means for locking an address, a method for executing a program including a series of instructions, said instructions including an interlocked operation defined by instructions between a lock instruction and an unlock instruction, said interlocked instructions including an instruction that accesses the external memory, said method comprising the steps of: (a) supplying the lock instruction from the program to the first computer processor; (b) executing the lock instruction in the first computer processor, including assigning a first value to a lock flag in the first computer processor and disabling external interrupts generated from sources external to the program, but not locking an address; (c) supplying the next instruction in the interlocked series of instructions to the first computer processor; (d) if in said step (c) said next instruction does not request a memory access and is not an unlock instruction, then executing said next instruction and repeating said step (c) to supply a next following instruction; (e) if in said step (c) said next instruction does request a memory access to a requested address, then asserting a lock signal from said first computer processor for locking the requested address such that the requested address can be accessed only by the task that requested the memory access, and then repeating said step (c) to supply a next following instruction; (f) if in said step (c) said next instruction is an unlock instruction, the executing said unlock instruction, including assigning a second value to the lock flag to indicate that unlocking has been requested, but not actually unlocking said requested address; and (g) following execution of the unlock instruction in the step (f), supplying a next instruction to the first computer processor, and if said next instruction requests a memory access, then enabling said external interrupts and de-asserting the lock signal to unlock the requested address.

Claim 16

The method of claim 13, further comprising a step (g) of: (g) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a memory access has not been requested in step (e) so that no address has been locked, and if an unlock instruction has not been executed in the step (g), then a second value is assigned to the lock flag indicating that locking is no longer requested.

Claim 17

The method of claim 14, wherein N is in an approximate range between twenty-five and thirty-five.

Claim 18

The method of claim 14, further comprising a step (h) of: (h) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a requested address has been locked in step (e) without unlocking in said step (g), then unlocking the requested address.

Claim 19

The method of claim 16, wherein N is in an approximate range between twenty-five and thirty-five.

Claim 20

The method of claim 13, wherein if a trap condition occurs following said step (b) but before unlocking the address, then the method further comprises the steps of: (h) assigning a second value to the lock flag to indicate that locking is not requested; (i) storing in a fault instruction register an address of the instruction that caused the trap condition; (j) clearing the lock signal so that the locked address is unlocked; (k) executing a trap handler routine that reads the address of the instruction that caused the trap condition and handles the trap condition; (l) scanning backward through the series of microinstructions to the lock instruction previously executed in said step (b), and (m) repeating said steps (b) through (f).

Claim 21

In a first computer processor connected through a bus to an external memory a second processor, and a address locking means for locking an address, a method for executing a program in the first computer processor, said program including a series of instructions said instructions including an interlocked operation defined by instructions between a lock instruction and an unlock instruction, said interlocked instructions including an instruction that accesses the external memory, said method comprising the steps of: (a) supplying the lock instruction from the program to the first computer processor; (b) executing the lock instruction in the first computer processor, including assigning a first value to a lock flag in a register in the first computer processor, and disabling external interrupts generated from sources external to the program, but not locking an address; (c) supplying the next instruction in the interlocked series of instructions to the first computer processor; (d) if in said step (c) said next instruction does not request a memory access and is not an unlock instruction, then executing said next instruction and repeating said step (c) to supply a next following instruction; (e) if in said step (c) said next instruction does request a memory access to a requested address, then asserting a lock signal from the first computer processor for locking the requested address such that the requested address can be accessed only by the task that requested the memory access, and then repeating said step (c) to supply a next following instruction; (f) if in said step (c) said next instruction is an unlock instruction, then performing the steps of: (f)(1) assigning a second value to the lock flag to indicate that unlocking has been requested, but not actually unlocking said requested address, and enabling said external interrupts, (f)(2) supplying and executing a next instruction in the series of instructions, (f)(3) if said next instruction does not request a memory access, then repeating said step (f)(2) to supply and execute a next following instruction, and (f)(4) if said next instruction requests a memory access, then deasserting the lock signal to unlock the requested address locked in the step (e); (g) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a memory access has not been requested in step (e) so that no address has been locked, and if an unlock instruction has not been executed in the step (g), then repeating said sub-steps (f)(1)-(f)(4); and (h) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a requested address has been locked in step (e) without unlocking in said step (f), then repeating said sub-steps (f)(1)-(f)(4).

Claim 22

In a first computer processor connected through a bus to an external memory a second processor, and a address locking means for locking an address, a method for executing a program in the first computer processor, said program including a series of instructions said instructions including an interlocked operation defined by instructions between a lock instruction and an unlock instruction, said interlocked instructions including an instruction that accesses the external memory, said method comprising the steps of: (a) supplying the lock instruction from the program to the first computer processor; (b) executing the lock instruction in the first computer processor, including assigning a first value to a lock flag in a register in the first computer processor, and disabling external interrupts generated from sources external to the program, but not locking an address; (c) supplying the next instruction in the interlocked series of instructions to the first computer processor; (d) if in said step (c) said next instruction does not request a memory access and is not an unlock instruction, then executing said next instruction and repeating said step (c) to supply a next following instruction; (e) if in said step (c) said next instruction does request a memory access to a requested address, then asserting a lock signal from the first computer processor for locking the requested address such that the requested address can be accessed only by the task that requested the memory access, and then repeating said step (c) to supply a next following instruction; (f) if in said step (c) said next instruction is an unlock instruction, then performing the steps of: (f)(1) assigning a second value to the lock flag to indicate that unlocking has been requested, but not actually unlocking said requested address, and enabling said external interrupts, (f)(2) supplying and executing a next instruction in the series of instructions, (f)(3) if said next instruction does not request a memory access, then repeating said step (f)(2) to supply and execute a next following instruction, and (f)(4) if said next instruction requests a memory access, then deasserting the lock signal to unlock the requested address locked in the step (e); (g) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a memory access has not been requested in step (e) so that no address has been locked, and if an unlock instruction has not been executed in the step (g), then repeating said sub-steps (f)(1)-(f)(4); and (h) if the step (c) is repeated more than N times following assigning a first value to the lock flag wherein N is a non-zero positive integer, and if a requested address has been locked in step (e) without unlocking in said step (f), then repeating said sub-steps (f)(1)-(f)(4).

Claim 23

The method of claim 19, wherein N is in an approximate range between twenty-five and thirty-five.

Claim 24

The method of claim 19, wherein if a trap condition occurs following said step (b) but before unlocking the address, then the method further comprises the steps of: (i) assigning a second value to the lock flag to indicate that locking is not requested; (j) storing in a fault instruction register an address of the instruction that caused the trap condition; (k) clearing the lock signal so that the locked address is unlocked; (l) executing a trap handler routine that reads the address of the instruction that caused the trap condition and handles the trap condition; (m) scanning backward through the series of microinstructions to the lock instruction previously executed in said step (b), and (n) repeating said steps (b) through (g).