US5523856A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing signal detecting and error-correcting apparatus
Assignee: Sony Corp
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Filing: 1993-11-22
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Granted: 1996-06-04
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Expires: 2013-11-22
Abstract
Abstract A synchronizing signal extracting apparatus comprising synchronizing signal detecting circuit for detecting a synchronizing signal of predetermined bits from entered digital data, synchronizing signal generating circuit adapted to be reset by an output of the synchronizing signal detecting circuit, the synchronizing signal generating circuit generating an output in a timing of said synchronizing signal, and synchronizing signal extracting circuit for outputting, as a synchronizing signal, a result of an OR operation performed on the output of said synchronizing signal detecting circuit and the output of said synchronizing signal generating circuit, the synchronizing signal extracting circuit changing a state thereof according to match/mismatch in timing between the output of said synchronizing signal detecting circuit and the output of said synchronizing signal generating circuit. The novel setup outputs correct synchronizing signals and data enable signal even if the detection of synchronizing signals is missed or erroneously made, reduces chances of the missed detection of synchronizing signals even when the signal-to-noise ratio of reproduced signal is poor at digital VTR variable-speed reproduction or high-speed search, and implements synchronizing signal extraction of high precision.
Inventors
- 👤 Masaki Kawano
- 👤 Takahito Seki
- 👤 Chihoko Takizawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:40
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/10; G; G11; G11B; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H04L7/08; H04L7/041; H04L7/042
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
129 words
A synchronizing signal detecting and error-correcting apparatus comprising: detecting means, responsive to an input signal which is comprised of an imprecise reproduction of a substantially periodic original digital synchronization signal, said detecting means having an adjustable bit error allowance, and being operable to detect said imprecise reproduction and to produce at least one output signal; generating means for generating a periodic output signal, the period of which depends upon said output signal from said detecting means; and error-correcting means which includes a state machine and is responsive to said detecting means and said generating means, for producing an adjustment signal to adjust said bit error allowance of said detecting means and for producing a substantially periodic corrected synchronization signal which is substantially synchronized with said original digital synchronizing signal.
Claim 2
Dependent Claim
129 words
A synchronizing signal detecting and error-correcting apparatus comprising: detecting means, responsive to an input signal which is comprised of an imprecise reproduction of a substantially periodic original digital synchronization signal, said detecting means having an adjustable bit error allowance, and being operable to detect said imprecise reproduction and to produce at least one output signal; generating means for generating a periodic output signal, the period of which depends upon said output signal from said detecting means; and error-correcting means which includes a state machine and is responsive to said detecting means and said generating means, for producing an adjustment signal to adjust said bit error allowance of said detecting means and for producing a substantially periodic corrected synchronization signal which is substantially synchronized with said original digital synchronizing signal.
Claim 3
Dependent Claim
24 words
The apparatus according to claim 1, wherein said error-correcting means produces a data enable signal which indicates the validity of said corrected synchronization signal.
Claim 4
Dependent Claim
39 words
The apparatus according to claim 1, wherein said state machine changes state depending upon whether an output signal from said detecting means and the periodic output signal from said generating means are synchronized or not synchronized with each other.
Claim 5
Dependent Claim
15 words
The apparatus according to claim 1, wherein said state machine has at least four states.
Claim 6
Dependent Claim
115 words
A synchronizing signal detecting and error-correcting apparatus comprising: detecting means, responsive to an input signal which is comprised of an imprecise reproduction of a substantially periodic original digital synchronization signal, for detecting said imprecise reproduction and for producing at least one output signal; generating means for generating a periodic output signal, the period of which depends upon the output signal from said detecting means; and error-correcting means, which includes a state machine, responsive to said detecting means and said generating means, for producing a substantially periodic corrected synchronization signal which is substantially synchronized with said original digital synchronizing signal and for producing a data enable signal which indicates the validity of said corrected synchronization signal.
Claim 7
Dependent Claim
115 words
A synchronizing signal detecting and error-correcting apparatus comprising: detecting means, responsive to an input signal which is comprised of an imprecise reproduction of a substantially periodic original digital synchronization signal, for detecting said imprecise reproduction and for producing at least one output signal; generating means for generating a periodic output signal, the period of which depends upon the output signal from said detecting means; and error-correcting means, which includes a state machine, responsive to said detecting means and said generating means, for producing a substantially periodic corrected synchronization signal which is substantially synchronized with said original digital synchronizing signal and for producing a data enable signal which indicates the validity of said corrected synchronization signal.
Claim 8
Dependent Claim
34 words
The apparatus according to claim 3, wherein said detecting means has an adjustable bit error allowance and said error-correcting means produces an adjustment signal to adjust said bit error allowance of said detecting means.
Claim 9
Dependent Claim
39 words
The apparatus according to claim 5, wherein said state machine changes state depending upon whether an output signal from said detecting means and the periodic output signal from said generating means are synchronized or not synchronized with each other.
Claim 10
Dependent Claim
15 words
The apparatus according to claim 5, wherein said state machine has at least four states.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |