DMD architecture and timing for use in a pulse-width modulated display system

Claim 2

A projection system comprising: a. a decimation processor comprising at least one input shift register, at least one shadow memory connected to said input shift register, and at least one output shift register connected to said shadow memory; b. at least one memory cell array for receiving data from said output shift register; and c. a spatial light modulator for receiving data from said memory cell array.

Claim 3

The projection system of claim 1 wherein said at least one memory cell array comprises a first and a second memory cell array.

Claim 4

The projection system of claim 2 further comprising a switchable bus connected between said decimation processor and said first and said second memory cell arrays, said bus for alternately connecting said first and said second memory cell array to said decimation processor.

Claim 5

The projection system of claim 2 further comprising a switchable bus connected between said first and said second memory cell arrays and said spatial light modulator, said bus for alternately connecting said first and said second memory cell array to said spatial light modulator.

Claim 6

The projection system of claim 2 further comprising: a first switchable bus connected between said decimation processor and said first and said second memory cell arrays, said first switchable bus for alternately connecting said first and said second memory cell array to said decimation processor; a second switchable bus connected between said first and said second memory cell arrays and said spatial light modulator, said second switchable bus for alternately connecting said first and said second memory cell array to said spatial light modulator; and wherein said first switchable bus and said second switchable bus are coordinated such that said first memory cell array receives data from said output shift register while said spatial light modulator receives data from said second memory cell array.

Claim 7

A decimation processor comprising: an n-bit wide input bus; an n-bit wide and m-bit deep input register for receiving a block of data from said input bus, said block of data being comprised of m input data words, each input data word being n-bits wide; an n-bit wide and m-bit deep shadow RAM for receiving said block of data from said input register; and an m-bit wide output bus for allowing said block of data to be read out of said shadow RAM in n output words wherein each said output word is m-bits wide and is comprised of one bit from each of said m input words.

Claim 8

A decimation processor comprising: an n-bit wide input bus; an n-bit wide and m-bit deep input register for receiving a block of data from said input bus, said block of data being comprised of m input data words, each input data word being n-bits wide; an n-bit wide and m-bit deep shadow RAM for receiving said block of data from said input register; and an m-bit wide output bus for allowing said block of data to be read out of said shadow RAM in n output words wherein each said output word is m-bits wide and is comprised of one bit from each of said m input words.

Claim 9

The decimation processor of claim 6 further comprising: an output register for receiving said m-bit output word in parallel from said output bus.

Claim 10

The decimation processor of claim 7 wherein said output register is an array of i output shift registers each being j-bits wide, said output shift registers receiving said m-bit output words in parallel from said output bus and outputting said m-bits in the form of j output data words, each said output data word being i-bits wide.

Claim 11

The decimation processor of claim 7 wherein said output register is a multiplexer.

Claim 12

The decimation processor of claim 7 wherein said output register is an array of i multiplexers, each said multiplexer being j-bits wide, said multiplexers receiving said m-bit output words in parallel from said output bus and outputting said m-bits in the form of j i-bit output data words.