Patent US5523252A successfully refreshed from Google Patents.
US5523252A
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US
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Method for fabricating and inspecting semiconductor integrated circuit substrate, and semi-finished product used for the sustrate
Assignee: Seiko Instruments Inc
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Filing: 1993-08-26
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Granted: 1996-06-04
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Expires: 2013-08-26
Abstract
Abstract The turn around time required for fabricating a semiconductor integrated circuit from initial conception through packaging may be dramatically reduced by testing the electrostatic integrity of the integrated circuit during fabrication rather than after packaging. In such a method, an electrostatic test device is formed on the same substrate on which the integrated circuit is formed. The test element may or may not comprise a portion of the integrated circuit itself, and a plurality of such test elements may in fact be formed along scribe lines in the wafer. Prior to dicing of individual integrated circuits, the electrostatic withstand capacity of the test element is determined by locating the power required to destroy the test element. The electrostatic destruction withstanding value of the integrated circuit is then derived from the maximum nondestruct power of the test element. Thus, an inspection step for electrostatic withstand capacity may be performed during fabrication, and need not await final packaging.
Inventors
- 👤 Yutaka Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:02
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/20; H10P74/207; H10P74/23; H10P74/27; H10P74/277
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
93 words
A method for fabricating an integrated circuit comprising the steps of: providing a semiconductor substrate; forming a semiconductor integrated circuit in the semiconductor substrate; forming a component evaluation area usable for evaluation of the semiconductor integrated circuit on the same semiconductor substrate; and electrically evaluating the component evaluation area to determine the electrostatic destruction withstanding ability thereof; wherein an electrostatic destruction withstanding value evaluation element is formed in the component evaluation area and the electrical evaluation includes the step of measurement of a destruction power of the electrostatic destruction withstanding value evaluation element.
Claim 2
Independent Claim
93 words
A method for fabricating an integrated circuit comprising the steps of: providing a semiconductor substrate; forming a semiconductor integrated circuit in the semiconductor substrate; forming a component evaluation area usable for evaluation of the semiconductor integrated circuit on the same semiconductor substrate; and electrically evaluating the component evaluation area to determine the electrostatic destruction withstanding ability thereof; wherein an electrostatic destruction withstanding value evaluation element is formed in the component evaluation area and the electrical evaluation includes the step of measurement of a destruction power of the electrostatic destruction withstanding value evaluation element.
Claim 3
Independent Claim
152 words
A method for inspecting a semiconductor integrated circuit prior to packaging of the integrated circuit comprising the steps of: providing a semiconductor substrate having a semiconductor integrated circuit and a component evaluation area usable for evaluation of the semiconductor integrated circuit on the same semiconductor substrate, the component evaluation area having an electrostatic destruction withstanding value evaluation element therein; applying various levels of voltages ranging from a nondestructive level to a destructive level to the electrostatic destruction withstanding value evaluation element and measuring the power consumed by the electrostatic destruction withstanding value evaluation element at each level of voltage applied to and current flowing through the electrostatic destruction withstanding value evaluation element; determining the power value when a highest nondestructive voltage is applied to the electrostatic destruction withstanding value evaluation element; and deciding whether or not the power value is adequate for the electrostatic destruction withstanding value of the semiconductor integrated circuit.
Claim 4
Independent Claim
152 words
A method for inspecting a semiconductor integrated circuit prior to packaging of the integrated circuit comprising the steps of: providing a semiconductor substrate having a semiconductor integrated circuit and a component evaluation area usable for evaluation of the semiconductor integrated circuit on the same semiconductor substrate, the component evaluation area having an electrostatic destruction withstanding value evaluation element therein; applying various levels of voltages ranging from a nondestructive level to a destructive level to the electrostatic destruction withstanding value evaluation element and measuring the power consumed by the electrostatic destruction withstanding value evaluation element at each level of voltage applied to and current flowing through the electrostatic destruction withstanding value evaluation element; determining the power value when a highest nondestructive voltage is applied to the electrostatic destruction withstanding value evaluation element; and deciding whether or not the power value is adequate for the electrostatic destruction withstanding value of the semiconductor integrated circuit.
Claim 5
Dependent Claim
55 words
A method for inspecting a semiconductor integrated circuit according to claim 2; wherein the step of determining the power value includes the steps of stopping the voltage supply to the electrostatic destruction withstanding value evaluation element when the power reaches a prescribed value, and deciding whether or not the power is in a nondestroyed area.
Claim 6
Dependent Claim
70 words
A method for inspecting a semiconductor integrated circuit according to claim 2; wherein the step of determining the power value includes the steps of applying current to the electrostatic destruction withstanding value evaluation element; increasing the applied current at a plurality of time intervals; measuring a voltage of the electrostatic destruction withstanding value evaluation element at each respective time interval; and calculating corresponding power levels at each respective time interval.
Claim 7
Dependent Claim
62 words
A method for inspecting a semiconductor integrated circuit according to claim 2; wherein the step of determining the power value includes the steps of applying current to the electrostatic destruction withstanding value evaluation element; increasing the applied current logarithmically at predetermined time intervals; measuring a corresponding voltage at each respective time interval; and obtaining corresponding power levels at each respective time interval.
Claim 8
Independent Claim
55 words
A method for fabricating a semiconductor integrated circuit comprising the steps of: providing a semiconductor substrate; forming a semiconductor integrated circuit on the substrate; and electrically inspecting the semiconductor integrated circuit by measuring the destroy power of a device in the integrated circuit and determining therefrom the electrostatic destroy withstanding value of the integrated circuit.
Claim 9
Independent Claim
55 words
A method for fabricating a semiconductor integrated circuit comprising the steps of: providing a semiconductor substrate; forming a semiconductor integrated circuit on the substrate; and electrically inspecting the semiconductor integrated circuit by measuring the destroy power of a device in the integrated circuit and determining therefrom the electrostatic destroy withstanding value of the integrated circuit.
Claim 10
Independent Claim
72 words
A method for inspecting a semiconductor integrated circuit comprising the steps of: applying a voltage to a single device of a semiconductor integrated circuit; measuring the power consumed by the device; stopping the supply of voltage at a power value less than a maximum destroy power; and determining whether or not said power value is in a nondestroyed area; whereby testing of the integrated circuit may be performed prior to packaging thereof.
Claim 11
Independent Claim
72 words
A method for inspecting a semiconductor integrated circuit comprising the steps of: applying a voltage to a single device of a semiconductor integrated circuit; measuring the power consumed by the device; stopping the supply of voltage at a power value less than a maximum destroy power; and determining whether or not said power value is in a nondestroyed area; whereby testing of the integrated circuit may be performed prior to packaging thereof.
Claim 12
Dependent Claim
65 words
A method for inspecting a semiconductor integrated circuit according to claim 7; wherein the step of measuring the power includes the steps of applying current to the device; increasing the current supply to the device at each of a plurality of time intervals; measuring a corresponding voltage across the device at each respective time interval; and determining corresponding power levels at each respective time interval.
Claim 13
Dependent Claim
66 words
A method for inspecting a semiconductor integrated circuit according to claim 7; wherein the step of measuring the power includes the steps of applying current to the device; logarithmically increasing the current supply to the device at each of a plurality of time intervals; measuring a corresponding voltage across the device at each respective time interval; and determining corresponding power levels at each respective time interval.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |