US5517542A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shift register with a transistor operating in a low duty cycle
Assignee: Vantiva SA
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Filing: 1995-03-06
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Granted: 1996-05-14
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Expires: 2015-03-06
Abstract
Abstract A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A third transistor responsive to an output signal of a stage downstream of the given stage applies a control signal to a gate electrode of the pull-down transistor to render the pull-down transistor conductive.
Inventors
- 👤 Ruquiya I. A. Huq
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:54
CPC Classifications
H; H03; H03K; H03K5/00; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
184 words
A shift register, comprising: a source of a plurality of phase shifted clock signals; a plurality of cascaded stages, a given one of said cascaded stages, including: a first transistor of a push-pull amplifier responsive to a first clock signal of said clock signals for generating an output pulse at an output of said given stage; an input section responsive to an output pulse developed at an output of a second of said cascaded stages when a clock signal that is phase shifted with respect to said first clock signal occurs for generating a control signal at a control electrode of said first transistor, said control signal conditioning said first transistor to generate said output pulse of said given stage when an active level of said first clock signal occurs; a second transistor of said push-pull amplifier coupled to said output of said given stage for clamping said output to an inactive level of said output pulse; and a switching, third transistor responsive to an output pulse of a stage downstream of said given stage for applying a control signal to said second transistor.
Claim 2
Dependent Claim
184 words
A shift register, comprising: a source of a plurality of phase shifted clock signals; a plurality of cascaded stages, a given one of said cascaded stages, including: a first transistor of a push-pull amplifier responsive to a first clock signal of said clock signals for generating an output pulse at an output of said given stage; an input section responsive to an output pulse developed at an output of a second of said cascaded stages when a clock signal that is phase shifted with respect to said first clock signal occurs for generating a control signal at a control electrode of said first transistor, said control signal conditioning said first transistor to generate said output pulse of said given stage when an active level of said first clock signal occurs; a second transistor of said push-pull amplifier coupled to said output of said given stage for clamping said output to an inactive level of said output pulse; and a switching, third transistor responsive to an output pulse of a stage downstream of said given stage for applying a control signal to said second transistor.
Claim 3
Dependent Claim
21 words
A shift register according to claim 1 wherein said control signal conditions said second transistor for conduction to clamp said output.
Claim 4
Dependent Claim
26 words
A shift register according to claim 1 wherein said first transistor is a pull-up transistor and said second transistor is a pull-down transistor of said amplifier.
Claim 5
Dependent Claim
151 words
A shift register, comprising: a source of a plurality of phase shifted clock signals; a plurality of cascaded stages, a given one of said cascaded stages, including: an output section responsive to a first clock signal of said clock signals for generating an output pulse at an output of said given stage when said first clock signal occurs; an input section responsive to an output pulse developed at an output of a second of said cascaded stages when a clock signal that is phase shifted with respect to said first clock signal occurs; a first transistor coupled to one of said input and output sections; a source of a control signal; and a second transistor responsive to an output pulse of a stage of said cascaded stages downstream of said given stage for applying said control signal to a control terminal of said first transistor to render said first transistor conductive.
Claim 6
Dependent Claim
151 words
A shift register, comprising: a source of a plurality of phase shifted clock signals; a plurality of cascaded stages, a given one of said cascaded stages, including: an output section responsive to a first clock signal of said clock signals for generating an output pulse at an output of said given stage when said first clock signal occurs; an input section responsive to an output pulse developed at an output of a second of said cascaded stages when a clock signal that is phase shifted with respect to said first clock signal occurs; a first transistor coupled to one of said input and output sections; a source of a control signal; and a second transistor responsive to an output pulse of a stage of said cascaded stages downstream of said given stage for applying said control signal to a control terminal of said first transistor to render said first transistor conductive.
Claim 7
Dependent Claim
50 words
A shift register according to claim 4 wherein said output pulse of said stage downstream of said given stage turns on said second transistor with a low duty cycle and said second transistor stores a charge in a capacitance that renders said first transistor conductive with a high duty cycle.
Claim 8
Dependent Claim
19 words
A shift register according to claim 4 wherein said first transistor is a pull-down transistor of said output section.
Claim 9
Dependent Claim
25 words
A shift register according to claim 4 wherein said first transistor is coupled to a control terminal of a pull-up transistor of said output section.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |