Ring-counter

Claim 2

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path, and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path; ''''n'''' said elements, ''''n'''' being an integer greater than 2, each one of said elements having a feed-back path extending from its data output terminal to the second data input terminal means upon each of n-2 consecutive elements immediately preceding said one element.

Claim 3

The ring counter of claim 1 wherein the second data input terminal means upon each of said elements is connected to said feedback paths through an OR-gate lens, the output of each of said OR-gate means being connected to said second data input terminal means, and the inputs to each of said OR-gate means being connected to each of said feedback paths which is to be connected to the respective one said terminal.

Claim 4

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path, and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having first and second cross-coupled field-effet effect transistors, the drain electrode of said first transistor connected to the gate electrode of said second transistor and the gate electrode of said first transistor connected to the drain electrode of said second transistor; a fifth transistor, the gate electrode of which is connected to means for connection to a pulse potential supply means; a third transistor having its source electrode connected to said means for connection to said pulse potential supply means and its gate electrode connected through said fifth transistor to first input terminal means; the gate electrode of said third transistor connected through capacitance means to means for connection to a reference ground potential point; the drain electrode of said first transistor connected through first load means to means for connection to a drain-potential supply rail and the drain electrode of said second transistor connected through second load means to means for connection to said drain-potential supply rail, the source electrodes of said first and second transistors connected to means for connection to a reference ground potential point; a fourth transistor connected in parallel with said second transistor across the source and drain electrodes thereof, said fourth transistor having its gate electrode connected to second input terminal means and capacitance means connected between the gate electrode of said fourth transistor and means for connection to a reference ground potential point; the drain electrode of said first transistor connected to the drain electrode of said third transistor and the drain electrode of said second transistor connected to output terminal means; said output terminal means of each said element being connected to said second input terminal means of the preceDing said element in said ring-counter and also connected to said first input terminal means of the succeeding said element in said ring-counter.

Claim 5

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path, and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having first and second cross-coupled field-effet effect transistors, the drain electrode of said first transistor connected to the gate electrode of said second transistor and the gate electrode of said first transistor connected to the drain electrode of said second transistor; a fifth transistor, the gate electrode of which is connected to means for connection to a pulse potential supply means; a third transistor having its source electrode connected to said means for connection to said pulse potential supply means and its gate electrode connected through said fifth transistor to first input terminal means; the gate electrode of said third transistor connected through capacitance means to means for connection to a reference ground potential point; the drain electrode of said first transistor connected through first load means to means for connection to a drain-potential supply rail and the drain electrode of said second transistor connected through second load means to means for connection to said drain-potential supply rail, the source electrodes of said first and second transistors connected to means for connection to a reference ground potential point; a fourth transistor connected in parallel with said second transistor across the source and drain electrodes thereof, said fourth transistor having its gate electrode connected to second input terminal means and capacitance means connected between the gate electrode of said fourth transistor and means for connection to a reference ground potential point; the drain electrode of said first transistor connected to the drain electrode of said third transistor and the drain electrode of said second transistor connected to output terminal means; said output terminal means of each said element being connected to said second input terminal means of the preceDing said element in said ring-counter and also connected to said first input terminal means of the succeeding said element in said ring-counter.

Claim 6

The ring-counter of claim 3 wherein said ring-counter contains ''''n'''' said elements - ''''n'''' being an integer greater than 2 - said output terminal means of each one of said elements being connected to said second input terminal means of each of the (n-2) consecutive elements immediately preceding said one element.

Claim 7

The ring counter of claim 4 wherein said first and second load means comprise eighth and ninth field-effect load transistors, respectively.

Claim 8

The ring-counter of claim 4 in integrated circuit form wherein said capacitance means comprise the gate to substrate capacitances of said third and fourth transistors.

Claim 9

The ring-counter of claim 4 wherein said capacitance means comprise the gate to substrate capacitances of said third and fourth transistors and each of said first and second load means comprises a field-effect load transistor.

Claim 10

The ring-counter of claim 3 wherein said first and second load means comprise eighth and ninth field-effect load transistors, respectively.

Claim 11

The ring-counter of claim 3 in integrated circuit form wherein said capacitance means comprise the gate to substrate capacitances of said third and fourth transistors.

Claim 12

The ring-counter of claim 3 wherein said capacitance means comprise the gate to substrate capacitances of said third and fourth transistors and each of said first and second load means comprises a field-effect load transistor.

Claim 13

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path, and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having first and second cross-coupled field-effect transistors, the drain electrode of said first transistor connected to the gate electrode of said second transistor and the gate electrode of said first transistor connected to the drain electrode of said second transistor; fifth and sixth transistors, the gate electrodes of which are connected to means for connection to a pulse potential supply means; a third transistor having its source electrode connected to said means for connection to said pulse potential supply means, its drain electrode connected to the source electrode of a seventh transistor and its gate electrode connected through said fifth transistor to first input terminal means; the gate electrode of said third transistor connected through capacitance means to means for connection to a reference ground potential point; the drain electrode of said first transistor connected through first load means to means for connection to a drain-potential supply rail and the drain electrode of said second transistor connected through second load means to means for connection to said drain-potential supply rail the source electrodes of said first and second transistors connected to means for connection to a reference ground potential point; a fourth transistor connected in parallel with said second transistor across the source and drain electrodes thereof, said fourth transistor having its gate electrode connected to second input terminal means and capacitance means connected between the gate electrode of said fourth transistor and means for connection to a reference ground potential point; the drain electrode of said first transistor connected to the drain electrode of said seventh transistor and the drain electrode of said second transistor connected to output terminal means.

Claim 14

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path, and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having first and second cross-coupled field-effect transistors, the drain electrode of said first transistor connected to the gate electrode of said second transistor and the gate electrode of said first transistor connected to the drain electrode of said second transistor; fifth and sixth transistors, the gate electrodes of which are connected to means for connection to a pulse potential supply means; a third transistor having its source electrode connected to said means for connection to said pulse potential supply means, its drain electrode connected to the source electrode of a seventh transistor and its gate electrode connected through said fifth transistor to first input terminal means; the gate electrode of said third transistor connected through capacitance means to means for connection to a reference ground potential point; the drain electrode of said first transistor connected through first load means to means for connection to a drain-potential supply rail and the drain electrode of said second transistor connected through second load means to means for connection to said drain-potential supply rail the source electrodes of said first and second transistors connected to means for connection to a reference ground potential point; a fourth transistor connected in parallel with said second transistor across the source and drain electrodes thereof, said fourth transistor having its gate electrode connected to second input terminal means and capacitance means connected between the gate electrode of said fourth transistor and means for connection to a reference ground potential point; the drain electrode of said first transistor connected to the drain electrode of said seventh transistor and the drain electrode of said second transistor connected to output terminal means.

Claim 15

The ring-counter of claim 11 wherein said ring-counter contains ''''n'''' said elements - ''''n'''' being an integer greater than 2 - said output terminal means of each one of said elements being connected via feed-back paths to said second input terminal means of each of the (n-2) consecutive elements immediately preceding said one element.

Claim 16

The ring-counter of claim 12 wherein said first and second load means comprise eighth and ninth field-effect load transistors, respectively.

Claim 17

The ring-counter of claim 12 in integrated circuit form wherein said capacitance means comprise the gate to substrate capacitances of said third, fourth and seventh transistors.

Claim 18

The ring-counter of claim 12 wherein said capacitance means comprise the gate to substrate capacitances of said third, fourth and seventh transistors and each of said first and second load means comprises a field-effect load transistor.

Claim 19

The ring-counter of claim 11 wherein said first and second load means comprise eighth and ninth field-effect load transistors, respectively.

Claim 20

The ring-counter of claim 11 in integrated circuit form wherein said capacitance means comprise the gate to substrate capacitances of said third, fourth and seventh transistors.

Claim 21

The ring-counter of claim 11 wherein said capacitance means comprise the gate to substrate capacitances of said third, fourth and seventh transistors and each of said first and second load means comprises a field-effect load transistor.

Claim 22

The ring-counter of claim 11 wherein the input terminal means upon each said element for receiving a plurality of feed-back paths as aforesaid is connected to said feed-back paths through an OR-gate means, the output of said OR-gate means connected to said input terminal means and the inputs to said OR-gate means connected to said feed-back paths.

Claim 23

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having tenth and eleventh cross-coupled field-effect transistors, the drain electrode of said tenth transistor connected through a thirteenth transistor to the gate electrode of said eleventh transistor, and the drain electrode of said eleventh transistor connected through a twelfth transistor to the gate electrode of said tenth transistor; the gate electrode of said twelfth transistor connected to the source electrode of said tenth transistor and to means for connection to a first pulse-potential supply means; the gate electrode of said thirteenth transistor connected to the source electrode of said eleventh transistor and to means for connection to a second pulse-potential supply means; said first and second pulse-potential supply means giving first and second non-overlapping pulse trains, respectively, swinging between enabling pulses for the transistors in said element to which they are applied and disabling pulses therefor, these being periods of time between consecutive first and second and second and first pulses during which both said pulse-potential supply means give disabling potentials; a fourteenth transistor in parallel with said tenth transistor and connected across the drain and source electrodes thereof, said drain electrodes of said tenth and fourteenth transistors being interconnected and connected through first load means to means for connection to said first pulse-potential supply means; a sixteenth transistor in parallel with said eleventh transistor and connected across the drain and source electrodes thereof, said drain electrodes of said eleventh and sixteenth transistors being interconnected and connected through a second load means to means for connection to Said second pulse-potential supply means; first and second input terminal means, said first input terminal means connected to the gate electrode of said fourteenth transistor through a fifteenth transistor and said second input terminal means connected to the gate electrode of said sixteenth transistor through a seventeenth transistor; the gate electrode of said fifteenth transistor connected to means for connection to said first pulse-potential supply means and the gate electrode of said seventeenth transistor connected to means for connection to said first pulse-potential supply means; capacitance means respectively connected between the gate electrodes of said tenth, eleventh, fourteenth and sixteenth transistors and means for connection to a reference ground potential point; output terminal means connected to the drain electrode of said sixteenth transistor; said output terminal means of each said element being connected to said second input terminal means of the preceding said element in said ring-counter and also connected to said first input terminal means of the succeeding said element in said ring-counter.

Claim 24

A ring-counter comprising a plurality of serially connected elements, each element having first and second data input terminal means and a data output terminal means, said data output terminal means of each element connected to one data input terminal means of the succeeding element to form a feed-forward path and said output terminal means of each element further connected to the second data input terminal means of the preceding element to form a feed-back path, each said element having tenth and eleventh cross-coupled field-effect transistors, the drain electrode of said tenth transistor connected through a thirteenth transistor to the gate electrode of said eleventh transistor, and the drain electrode of said eleventh transistor connected through a twelfth transistor to the gate electrode of said tenth transistor; the gate electrode of said twelfth transistor connected to the source electrode of said tenth transistor and to means for connection to a first pulse-potential supply means; the gate electrode of said thirteenth transistor connected to the source electrode of said eleventh transistor and to means for connection to a second pulse-potential supply means; said first and second pulse-potential supply means giving first and second non-overlapping pulse trains, respectively, swinging between enabling pulses for the transistors in said element to which they are applied and disabling pulses therefor, these being periods of time between consecutive first and second and second and first pulses during which both said pulse-potential supply means give disabling potentials; a fourteenth transistor in parallel with said tenth transistor and connected across the drain and source electrodes thereof, said drain electrodes of said tenth and fourteenth transistors being interconnected and connected through first load means to means for connection to said first pulse-potential supply means; a sixteenth transistor in parallel with said eleventh transistor and connected across the drain and source electrodes thereof, said drain electrodes of said eleventh and sixteenth transistors being interconnected and connected through a second load means to means for connection to Said second pulse-potential supply means; first and second input terminal means, said first input terminal means connected to the gate electrode of said fourteenth transistor through a fifteenth transistor and said second input terminal means connected to the gate electrode of said sixteenth transistor through a seventeenth transistor; the gate electrode of said fifteenth transistor connected to means for connection to said first pulse-potential supply means and the gate electrode of said seventeenth transistor connected to means for connection to said first pulse-potential supply means; capacitance means respectively connected between the gate electrodes of said tenth, eleventh, fourteenth and sixteenth transistors and means for connection to a reference ground potential point; output terminal means connected to the drain electrode of said sixteenth transistor; said output terminal means of each said element being connected to said second input terminal means of the preceding said element in said ring-counter and also connected to said first input terminal means of the succeeding said element in said ring-counter.

Claim 25

The ring-counter of claim 20 wherein said ring-counter contains ''''n'''' said elements - ''''n'''' being an integer greater than 2 - said output terminal means of each one of said elements being connected to said second input terminal means of each of the (n-2) consecutive elements immediately preceding said one element.

Claim 26

The ring-counter of claim 21 wherein said first and second load means comprise eighteenth and nineteenth field-effect load transistors, respectively.

Claim 27

The ring-counter of claim 21 in integrated circuit form wherein said capacitance means respectively comprise the gate to substrate capacitances of said tenth, eleventh, fourteenth and sixteenth transistors.

Claim 28

The ring-counter of claim 20 in integrated circuit form wherein said capacitance means respectively comprise the gate to substrate capacitances of said tenth, eleventh, fourteenth and sixteenth transistors and said first and second load means comprise eighteenth and nineteenth field-effect load transistors, respectively.

Claim 29

The ring-counter of claim 21 wherein the input terminal means upon each said element for receiving a plurality of feed-back paths as aforesaid is connected to said feed-back paths as aforesaid is connected to said feed-back paths through an OR-gate means, the output of said OR-gate means connected to said input terminal means and the inputs to said OR-gate means connected to said feed-back paths.

Claim 30

The ring-counter of claim 20 wherein said first and second load means comprise eighteenth and nineteenth field-effect load transistors, respectively.

Claim 31

The ring-counter of claim 20 in integrated circuit form wherein said capacitance means respectively comprise the gate to substrate capacitances of said tenth, eleventh, fourteenth and sixteenth transistors.

Claim 32

The ring-counter of claim 20 in integrated circuit form wherein said capacitance means respectively comprise the gate to substrate capacitances of said tenth, eleventh, fourteenth and sixteenth transistors of said first and second load means comprise eighteenth and nineteenth field-effect load transistors, respectively.