Redundant maintenance architecture

Claim 1

An apparatus for detecting and correcting faults within a computer system comprising; a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces coupling said plurality of computer modules to said secondary maintenance processor; f. a decoder coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; g. an Or-Gate coupled to said decoder for polling the outputs of said decoder; h. a timer coupled to said Or-Gate for timing a predetermined time period wherein said timer expires after the predetermined time period if not reset by said Or-Gate during the predetermined time period; and i. a lock/clear circuit coupled to said timer for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said timer expires.

Claim 2

An apparatus for detecting and correcting faults within a computer system comprising; a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces coupling said plurality of computer modules to said secondary maintenance processor; f. a decoder coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; g. an Or-Gate coupled to said decoder for polling the outputs of said decoder; h. a timer coupled to said Or-Gate for timing a predetermined time period wherein said timer expires after the predetermined time period if not reset by said Or-Gate during the predetermined time period; and i. a lock/clear circuit coupled to said timer for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said timer expires.

Claim 3

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces coupling said plurality of computer modules to said secondary maintenance processor; f. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; g. polling means coupled to said decoding means for polling the outputs of said decoding means; h. timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and i. switching means coupled to said timing means and further coupled to said secondary maintenance processor for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary maintenance interfaces when said timing means expires.

Claim 4

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces coupling said plurality of computer modules to said secondary maintenance processor; f. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; g. polling means coupled to said decoding means for polling the outputs of said decoding means; h. timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and i. switching means coupled to said timing means and further coupled to said secondary maintenance processor for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary maintenance interfaces when said timing means expires.

Claim 5

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules having a first processing complex and a second processing complex; d. said first processing complex coupled to a first power domain and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; e. a secondary maintenance processor; f. a plurality of secondary maintenance interfaces; g. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; h. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; i. polling means coupled to said decoding means for polling the outputs of said decoding means; j. a timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and k. switching means coupled to said timing means for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said timing means expires.

Claim 6

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules having a first processing complex and a second processing complex; d. said first processing complex coupled to a first power domain and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; e. a secondary maintenance processor; f. a plurality of secondary maintenance interfaces; g. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; h. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; i. polling means coupled to said decoding means for polling the outputs of said decoding means; j. a timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and k. switching means coupled to said timing means for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said timing means expires.

Claim 7

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules each having a first processing complex and a plurality of second processing complexes; d. said first processing complex coupled to a first power domain and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; e. a plurality of secondary maintenance processors; f. a plurality of secondary maintenance interfaces; g. each particular one of said plurality of second processing complexes coupled to a particular one of a plurality of second power domains and further coupled to a particular one of said plurality of secondary maintenance processors via said plurality of secondary maintenance interfaces; h. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; i. polling means coupled to said decoding means for polling the outputs of said decoding means; a timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and k. switching means coupled to said timing means for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said one of said plurality of secondary maintenance processors and said plurality of secondary interfaces when said timing means expires.

Claim 8

An apparatus for detecting and correcting faults within a computer system comprising: a. a primary maintenance processor; b. a plurality of primary maintenance interfaces; c. a plurality of computer modules each having a first processing complex and a plurality of second processing complexes; d. said first processing complex coupled to a first power domain and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; e. a plurality of secondary maintenance processors; f. a plurality of secondary maintenance interfaces; g. each particular one of said plurality of second processing complexes coupled to a particular one of a plurality of second power domains and further coupled to a particular one of said plurality of secondary maintenance processors via said plurality of secondary maintenance interfaces; h. decoding means coupled to said primary maintenance processor via said plurality of primary maintenance interfaces for decoding a predetermined set of control bits; i. polling means coupled to said decoding means for polling the outputs of said decoding means; a timing means coupled to said polling means for timing a predetermined time period wherein said timing means expires after the predetermined time period if not reset by said polling means during the predetermined time period; and k. switching means coupled to said timing means for switching control from said primary maintenance processor and said plurality of primary maintenance interfaces to said one of said plurality of secondary maintenance processors and said plurality of secondary interfaces when said timing means expires.

Claim 9

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces; f. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain and a second timing clock coupled to said second power domain; h. detecting means coupled to the primary maintenance processor for comparing said first timing clock and said second timing clock; i. service request means coupled to said detecting means for indicating a fault if said first timing clock and said second timing clock do not compare; and j. switching means coupled to said service request means and further coupled to the primary maintenance processor and said secondary maintenance processor for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said service request means indicates said fault.

Claim 10

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces; f. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain and a second timing clock coupled to said second power domain; h. detecting means coupled to the primary maintenance processor for comparing said first timing clock and said second timing clock; i. service request means coupled to said detecting means for indicating a fault if said first timing clock and said second timing clock do not compare; and j. switching means coupled to said service request means and further coupled to the primary maintenance processor and said secondary maintenance processor for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said service request means indicates said fault.

Claim 11

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces; f. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain and a second timing clock coupled to said second power domain; h. a detecting circuit coupled to the primary maintenance processor for comparing said first timing clock and said second timing clock; i. a service request circuit coupled to said detecting circuit for indicating a fault if said first timing clock and said second timing clock do not compare; and j. a switching circuit coupled to said service request circuit and further coupled to the primary maintenance processor and said secondary maintenance processor for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said service request circuit indicates said fault.

Claim 12

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a secondary maintenance processor; e. a plurality of secondary maintenance interfaces; f. said second processing complex coupled to a second power domain and further coupled to said secondary maintenance processor via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain and a second timing clock coupled to said second power domain; h. a detecting circuit coupled to the primary maintenance processor for comparing said first timing clock and said second timing clock; i. a service request circuit coupled to said detecting circuit for indicating a fault if said first timing clock and said second timing clock do not compare; and j. a switching circuit coupled to said service request circuit and further coupled to the primary maintenance processor and said secondary maintenance processor for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said secondary maintenance processor and said plurality of secondary interfaces when said service request circuit indicates said fault.

Claim 13

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a plurality of secondary maintenance processors; e. a plurality of secondary maintenance interfaces; f. each particular one of said plurality of second processing complexes coupled to a particular one of a plurality of second power domains and further coupled to a particular one of said plurality of secondary maintenance processors via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain; h. each particular one of a plurality of second timing clocks coupled to said particular one of said plurality of second power domains; i. detecting means coupled to the primary maintenance processor for comparing said first timing clock and said particular one of said plurality of second timing clocks; j. service request means coupled to said detecting means for indicating a fault if said first timing clock and said particular one of said plurality of second timing clocks do not compare; and k. switching means coupled to said service request means and further coupled to the primary maintenance processor and said particular one of a plurality of secondary maintenance processors for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said particular one of a plurality of secondary maintenance processors and said plurality of secondary interfaces when said service request means indicates said fault.

Claim 14

An apparatus having a primary maintenance processor, a plurality of computer modules, and a plurality of primary interfaces coupling the primary maintenance processor to the plurality of computer modules, the improvement comprising: a. the plurality of computer modules each having a first processing complex and a second processing complex; b. said first processing complex coupled to said second processing complex via a clock maintenance interface; c. said first processing complex further coupled to a first power domain, and further coupled to said primary maintenance processor via said plurality of primary maintenance interfaces; d. a plurality of secondary maintenance processors; e. a plurality of secondary maintenance interfaces; f. each particular one of said plurality of second processing complexes coupled to a particular one of a plurality of second power domains and further coupled to a particular one of said plurality of secondary maintenance processors via said plurality of secondary maintenance interfaces; g. a first timing clock coupled to said first power domain; h. each particular one of a plurality of second timing clocks coupled to said particular one of said plurality of second power domains; i. detecting means coupled to the primary maintenance processor for comparing said first timing clock and said particular one of said plurality of second timing clocks; j. service request means coupled to said detecting means for indicating a fault if said first timing clock and said particular one of said plurality of second timing clocks do not compare; and k. switching means coupled to said service request means and further coupled to the primary maintenance processor and said particular one of a plurality of secondary maintenance processors for switching control from the primary maintenance processor and the plurality of primary maintenance interfaces to said particular one of a plurality of secondary maintenance processors and said plurality of secondary interfaces when said service request means indicates said fault.