Patent US1264772A successfully refreshed from Google Patents.
Patent US5514950A successfully refreshed from Google Patents.
US5514950A
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Differential pair arrangement
Assignee: Alcatel Lucent NV
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Filing: 1994-03-15
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Granted: 1996-05-07
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Expires: 2014-03-15
Abstract
Abstract A differential pair arrangement is disclosed which includes between the poles of a DC supply source the series connection of two parallel first branches and a common second branch. Each first branch includes the series connection of a first impedance Q2, Q3, RL/ Q2', Q3', RL', a main path of a transistor Q1/ Q1'and a second impedance RE/RE', the control electrodes of transistors Q1/ Q1' constituting respective input terminals IN1/ IN2 of the arrangement. The second branch includes a first current source (CCS). The arrangement further includes two third branches between the DC supply source poles, each consisting of the series connection of a second current source ICS/ICS', a respective transistor main path and a resistive impedance means R11, S11, R12, S12/ R11', S11', R12', S12'. These third branches result in an increased DC current through the corresponding transistor, thereby increasing the linearity of the arrangement, whilst the DC current through the first and second impedances does not increase, thereby not increasing the needed supply voltage nor the offset voltage of the arrangement.
Inventors
- 👤 Joannes M. J. Sevenhans
- 👤 Mark G. S. J. Van Paemel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:00
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3211; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45085; H03F3/45089; H03F3/72; H03F2203/00; H03F2203/45; H03F2203/45048; H03F2203/45311; H03F2203/45322; H03F2203/45362; H03F2203/45466; H03F2203/45471; H03F2203/45504
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
293 words
A differential pair arrangement included between a first (VCC) and a second (VSS) pole of a DC supply source the series connection of two parallel individual first branches and a common second branch, each of said first branches including the series connection of a first impedance (Q2, Q3, RL/Q2', Q3', RL'), a main path of a transistor (Q1/Q2') and a second impedance (RE/RE'), with the control electrodes of said transistors (Q1/Q1') constituting respective input terminals (IN1/IN2) of said differential pair arrangement, and said second branch including a common first current source (CCS), characterized in that it further includes between said first (VCC) and second (VSS) poles two third branches, the series connection of two parallel individual fourth branches, a common fifth branch, and two sixth branches, each of said third branches including the series connection of an individual second current source (ICS/ICS'), a respective one of said main paths and a resistive impedance means (R11, S11, R12, S12/R11', S11', R12', S12') each of said fourth branches including the series connection of said first impedance (Q2, Q3, RL/Q2', Q3', RL'), a main path of a second transistor (Q1a Q1a') and a third impedance (REa/REa'), with the control electrode of the respective second transistors (Q1a/Q1a') connected to the respective ones of said input terminals (IN1/IN2), said fifth branch including a common third current source (CCSa), and each of said sixth branches consisting of the series connection of a respective one of said second current sources (ICS/ICS'), a respective one of said second transistor main paths and a second resistive impedance means (R1a, S1a/R1a', S1a'), said second resistive impedance means (R1a, S1a/R1a', S1a') and said third current source (CCSa) being sized so as to be able to be cut off by a gain control signal (GAIN).
Claim 2
Dependent Claim
293 words
A differential pair arrangement included between a first (VCC) and a second (VSS) pole of a DC supply source the series connection of two parallel individual first branches and a common second branch, each of said first branches including the series connection of a first impedance (Q2, Q3, RL/Q2', Q3', RL'), a main path of a transistor (Q1/Q2') and a second impedance (RE/RE'), with the control electrodes of said transistors (Q1/Q1') constituting respective input terminals (IN1/IN2) of said differential pair arrangement, and said second branch including a common first current source (CCS), characterized in that it further includes between said first (VCC) and second (VSS) poles two third branches, the series connection of two parallel individual fourth branches, a common fifth branch, and two sixth branches, each of said third branches including the series connection of an individual second current source (ICS/ICS'), a respective one of said main paths and a resistive impedance means (R11, S11, R12, S12/R11', S11', R12', S12') each of said fourth branches including the series connection of said first impedance (Q2, Q3, RL/Q2', Q3', RL'), a main path of a second transistor (Q1a Q1a') and a third impedance (REa/REa'), with the control electrode of the respective second transistors (Q1a/Q1a') connected to the respective ones of said input terminals (IN1/IN2), said fifth branch including a common third current source (CCSa), and each of said sixth branches consisting of the series connection of a respective one of said second current sources (ICS/ICS'), a respective one of said second transistor main paths and a second resistive impedance means (R1a, S1a/R1a', S1a'), said second resistive impedance means (R1a, S1a/R1a', S1a') and said third current source (CCSa) being sized so as to be able to be cut off by a gain control signal (GAIN).
Claim 3
Dependent Claim
40 words
A differential pair arrangement according to claim 1 characterized in that at least one of said resistive impedance means (R11, S11, R12, S12; R11', S11'; R12', S12'; R1a, S1a; R1a', S1a') includes a resistor (R11, R12, R11', R12', R1a, R1a').
Claim 4
Dependent Claim
58 words
A differential pair arrangement according to claim 1 characterized in that the total current flowing through the respective ones of said resistive impedance means (R11, S11, R12, S12, R1a, S1a /R11', S11', R12', S12', R1a', S1a') belonging to branches with a same second current source (ICS/ICS'), substantially equals the current provided by said same second current source (ICS/ICS').
Claim 5
Dependent Claim
51 words
A differential pair arrangement according to claim 1 characterized in that at least one of said second current sources (ICS, ICS') and resistive impedance means (R11, S11, R12, S12; R1a, S1a; R11', S11', R12', S12'; R1a', S1a') is controlled by a linearity control signal (LIN) tuning the current provided by them.
Claim 6
Dependent Claim
37 words
A differential pair arrangement according to claim 1, characterized in that at least one of said first, second and third current sources (CCS, ICS, ICS', CCSa) includes means for supplying a current which increases with increasing temperature.
Claim 7
Dependent Claim
183 words
A differential pair arrangement according to claim 1, characterized in that said first impedance (Q2, Q3, RL/Q2', Q3', RL') of each of said first branches includes two parallel seventh branches, a first one of which includes the series connection of a load impedance (RL/ RL') and a main path of a third transistor (Q2/ Q2'), and a second one of which includes the series connection of the load impedance (RL'/ RL) included in the other one of said first branches, and a main path of a fourth transistor (Q3/ Q3'), the control electrodes of said third transistors (Q2/ Q2') of both said seventh branches being interconnected as well as those of said fourth transistors (Q3/ Q3') and constituting respective third and fourth input terminals (BL01, BL02) of said differential pair arrangement, the junction points of the load impedances (RL/ RL') with the respective third transistors (Q2/ Q2') constituting respective first and second output terminals (OUT1/ OUT2) of said differential pair arrangement, and that a signal with a substantially constant common mode voltage is applied across said third and fourth input terminals (BL01, BL02).
Claim 8
Dependent Claim
52 words
A differential pair arrangement according to claim 6, characterized in that a modulating signal is applied across said first and second input terminals (IN1, IN2), thereby producing across said first and second output terminals (OUT1, OUT2) a modulated signal which is the product of said modulating signal and said first mentioned signal.
Claim 9
Dependent Claim
21 words
Differential pair arrangement according to claim 6, characterized in that said second current source (ICS/ ICS') is constituted by a resistor.
Claim 10
Dependent Claim
45 words
A differential pair arrangement according to claim 6, characterized in that said transistors (Q1, Q1', Q1a, Q1a', Q2, Q2', Q3, Q3') are bipolar transistors, said main paths being constituted by the collector emitter path thereof and said control electrodes being constituted by the base thereof.
Claim 11
Dependent Claim
45 words
A differential pair arrangement according to claim 1, characterized in that said transistors (Q1, Q1', Q1a, Q1a', Q2, Q2', Q3, Q3') are bipolar transistors, said main paths being constituted by the collector emitter path thereof and said control electrodes being constituted by the base thereof.
References Cited (Backward Citations)
JPS56149803A
Cited
EP0040274A1
Cited
JPS5827407A
Cited
US4480337A
Cited
EP0090329A1
Cited
US4525663A
Cited
US4814724A
Cited
EP0356556A1
Cited
US5099205A
Cited
US5404097A
Cited
US5373228A
Cited
US5424681A
Cited
US5374897A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |