Balanced, high-speed differential input stage for Op-amps

Claim 2

An amplifier circuit, comprising: an input terminal; a first emitter follower having a base terminal connected to the input terminal, having a collector terminal connected to a first voltage supply terminal, and having an emitter terminal; a second emitter follower having a base terminal connected to the input terminal, having a collector terminal connected to the first voltage supply terminal, and having an emitter terminal; a first diode-connected transistor having an emitter terminal connected to the emitter terminal of the second emitter follower, said first diode-connected transistor having a base terminal and a collector terminal connected together; a current source having a first terminal connected to the base and collector terminals of the first diode-connected transistor, and having a second terminal connected to a second voltage terminal; and an output drive transistor having a base terminal connected to the base and collector terminals of the first diode-connected transistor, having an emitter terminal connected to the emitter terminal of the first emitter follower, and having a collector terminal for providing an output load current.

Claim 3

The amplifier of claim 1 wherein the first and second emitter followers are PNP transistors and wherein the first diode-connected transistor and the output drive transistor are NPN transistors.

Claim 4

The amplifier of claim 1 wherein the first and second emitter followers are NPN transistors and wherein the first diode-connected transistor and the output drive transistor are PNP transistors.

Claim 5

The amplifier of claim 1 wherein the first and the second emitter followers are formed as a composite transistor with two emitter regions, one collector region, and one base region.

Claim 6

A differential input circuit, comprising: a first half of a differential input circuit, including: a first differential input voltage terminal; a first emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to a first voltage terminal, and having an emitter terminal connected to a first terminal of an emitter resistor; a second emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal; a first diode-connected transistor having an emitter terminal connected to the emitter terminal of the second emitter follower and having a base terminal and a collector terminal connected together; a first current source having a first output terminal connected to the base and collector terminals of the first diode-connected transistor and having a second input terminal connected to a second voltage terminal; and a first output drive transistor having a base terminal connected to the base and collector terminals of the first diode-connected transistor, having an emitter terminal connected to a first terminal of an emitter resistor and to the emitter terminal of the first emitter follower, and having a collector terminal for providing a first differential output current; and a second half of a differential input circuit, including: a second differential input voltage terminal; a third emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal connected to a second terminal of the emitter resistor; a fourth emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal; a second diode-connected transistor having an emitter terminal connected to the emitter terminal of the fourth emitter follower and having a base terminal and a collector terminal connected together; a second current source having a first output terminal connected to the base and collector terminals of the second diode-connected transistor, and having a second terminal connected to the second voltage terminal; and a second output drive transistor having a base terminal connected to the base and collector terminals of the second diode-connected transistor, having an emitter terminal connected to the second terminal of the emitter resister and to the emitter of the third emitter follower, and having a collector terminal for providing a second differential output current.

Claim 7

A differential input circuit, comprising: a first half of a differential input circuit, including: a first differential input voltage terminal; a first emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to a first voltage terminal, and having an emitter terminal connected to a first terminal of an emitter resistor; a second emitter follower having a base terminal connected to the first differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal; a first diode-connected transistor having an emitter terminal connected to the emitter terminal of the second emitter follower and having a base terminal and a collector terminal connected together; a first current source having a first output terminal connected to the base and collector terminals of the first diode-connected transistor and having a second input terminal connected to a second voltage terminal; and a first output drive transistor having a base terminal connected to the base and collector terminals of the first diode-connected transistor, having an emitter terminal connected to a first terminal of an emitter resistor and to the emitter terminal of the first emitter follower, and having a collector terminal for providing a first differential output current; and a second half of a differential input circuit, including: a second differential input voltage terminal; a third emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal connected to a second terminal of the emitter resistor; a fourth emitter follower having a base terminal connected to the second differential input terminal, having a collector terminal connected to the first voltage terminal, and having an emitter terminal; a second diode-connected transistor having an emitter terminal connected to the emitter terminal of the fourth emitter follower and having a base terminal and a collector terminal connected together; a second current source having a first output terminal connected to the base and collector terminals of the second diode-connected transistor, and having a second terminal connected to the second voltage terminal; and a second output drive transistor having a base terminal connected to the base and collector terminals of the second diode-connected transistor, having an emitter terminal connected to the second terminal of the emitter resister and to the emitter of the third emitter follower, and having a collector terminal for providing a second differential output current.

Claim 8

The differential input circuit of claim 5 wherein the first, second, third, and fourth emitter followers are PNP transistors, wherein the first and the second diode-connected transistors are NPN transistors, and wherein the first and the second output drive transistors are NPN transistors.

Claim 9

The differential input circuit of claim 5 wherein the first, second, third, and fourth emitter followers are NPN transistors, wherein the first and the second diode-connected transistors are PNP transistors, and wherein the first and the second output drive transistors are PNP transistors.

Claim 10

The differential input circuit of claim 5 wherein a resistor and a capacitor are connected in series between the terminals of the emitter terminals to provide high-frequency boost for the input differential pair.

Claim 11

The amplifier of claim 5 wherein the first and the second emitter followers are formed as a composite transistor with two emitter regions, one collector region, and one base region.

Claim 12

The differential input circuit of claim 5 wherein the respective collector terminals of the first and second output drive transistors are connected to respective emitter terminals of two common base transistors such that the first and second output drive transistors and the two common base transistors form a balanced folded cascade configuration.

Claim 13

A balanced differential input circuit, comprising: a first PNP transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a negative voltage supply terminal, and having emitter terminal; a first NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first NPN transistor is connected to the emitter terminal of the first PNP transistor; a first current source, having an output terminal connected to the base and collector terminals of the first NPN transistor and having an input terminal connected to a positive voltage supply terminal; a second PNP transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a second NPN transistor having its base terminal coupled to the base terminal of the second PNP transistor, having an emitter terminal coupled to the emitter terminal of the second PNP transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal; a third PNP transistor having a base terminal connected to an inverting input terminal having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a third NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third NPN transistor is connected to the emitter terminal of the third PNP transistor; a second current source, having an output terminal connected to the base and collector terminals of the third NPN transistor and having an input terminal connected to the positive voltage supply terminal; a fourth PNP transistor having a base terminal connected to the inverting input terminal for the operational amplifier, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a fourth NPN transistor having its base terminal coupled to the base terminal of the third NPN transistor, having an emitter terminal coupled to the emitter terminal of the fourth PNP transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.

Claim 14

A balanced differential input circuit, comprising: a first PNP transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a negative voltage supply terminal, and having emitter terminal; a first NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first NPN transistor is connected to the emitter terminal of the first PNP transistor; a first current source, having an output terminal connected to the base and collector terminals of the first NPN transistor and having an input terminal connected to a positive voltage supply terminal; a second PNP transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a second NPN transistor having its base terminal coupled to the base terminal of the second PNP transistor, having an emitter terminal coupled to the emitter terminal of the second PNP transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal; a third PNP transistor having a base terminal connected to an inverting input terminal having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a third NPN transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third NPN transistor is connected to the emitter terminal of the third PNP transistor; a second current source, having an output terminal connected to the base and collector terminals of the third NPN transistor and having an input terminal connected to the positive voltage supply terminal; a fourth PNP transistor having a base terminal connected to the inverting input terminal for the operational amplifier, having a collector terminal connected to the negative voltage supply terminal, and having an emitter terminal; a fourth NPN transistor having its base terminal coupled to the base terminal of the third NPN transistor, having an emitter terminal coupled to the emitter terminal of the fourth PNP transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.

Claim 15

The balanced differential input circuit of claim 11 wherein the first and third PNP transistors have emitters with a given area and wherein the second and fourth PNP transistors have emitters with areas which are n times the given area of the first and the second PNP transistors.

Claim 16

The balanced differential input circuit of claim 11 wherein the first, and third NPN transistors have emitters with a given area and wherein the second and fourth NPN transistors have emitters with areas which are n times the given areas of the first and the second NPN transistors.

Claim 17

The balanced differential input circuit of claim 11 wherein the emitter impedance includes a first resistor.

Claim 18

The balanced differential input circuit of claim 11 including another resistor and a capacitor connected in series between the terminals of the emitter impedance terminals to provide high-frequency boost for the input circuit.

Claim 19

The balanced differential input circuit of claim 11 wherein the first and the second PNP transistors are formed as a composite transistor with two emitter regions, one collector region, and one base region and wherein the third and fourth PNP transistors are also formed as a composite transistor with two emitter regions, one collector region, and one base region.

Claim 20

A balanced differential input circuit, comprising: a first NPN transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal; a first PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first PNP transistor is connected to the emitter terminal of the first NPN transistor; a first current source, having an input terminal connected to the base and collector terminals of the first PNP transistor and having an output terminal connected to a negative voltage supply terminal; a second NPN transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal; a second PNP transistor having its base terminal coupled to the base terminal of the first PNP transistor, having an emitter terminal coupled to the emitter terminal of the second NPN transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal; a third NPN transistor having a base terminal connected to an inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal; a third PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third PNP transistor is connected to the emitter terminal of the third NPN transistor; a second current source, having an input terminal connected to the base and collector terminals of the third PNP transistor and having an output terminal connected to the negative voltage supply terminal; a fourth NPN transistor having a base terminal connected to the inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal; a fourth PNP transistor having its base terminal coupled to the base terminal of the third PNP transistor having an emitter terminal coupled to the emitter terminal of the fourth NPN transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.

Claim 21

A balanced differential input circuit, comprising: a first NPN transistor having a base terminal connected to a non-inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal; a first PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the first PNP transistor is connected to the emitter terminal of the first NPN transistor; a first current source, having an input terminal connected to the base and collector terminals of the first PNP transistor and having an output terminal connected to a negative voltage supply terminal; a second NPN transistor having a base terminal connected to the non-inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal; a second PNP transistor having its base terminal coupled to the base terminal of the first PNP transistor, having an emitter terminal coupled to the emitter terminal of the second NPN transistor and coupled to one terminal of an emitter impedance, and having a collector terminal connected to a first differential output terminal; a third NPN transistor having a base terminal connected to an inverting input terminal, having a collector terminal connected to a positive voltage supply terminal, and having an emitter terminal; a third PNP transistor having its base and collector terminals connected together and having an emitter terminal, where the emitter terminal of the third PNP transistor is connected to the emitter terminal of the third NPN transistor; a second current source, having an input terminal connected to the base and collector terminals of the third PNP transistor and having an output terminal connected to the negative voltage supply terminal; a fourth NPN transistor having a base terminal connected to the inverting input terminal, having a collector terminal connected to the positive voltage supply terminal, and having an emitter terminal; a fourth PNP transistor having its base terminal coupled to the base terminal of the third PNP transistor having an emitter terminal coupled to the emitter terminal of the fourth NPN transistor and coupled to another terminal of the emitter impedance, and having a collector terminal connected to a second differential output terminal.

Claim 22

The balanced differential input circuit of claim 17 wherein the first, second NPN transistors have emitters with a given area and wherein the third and fourth NPN transistors have emitters with areas which are n times the given area of the first and the second NPN transistors.

Claim 23

The balanced differential input circuit of claim 17 wherein the first, second PNP transistors have emitters with a given area and wherein the third and fourth PNP transistors have emitters with areas which are n times the given areas of the first and the second PNP transistors.

Claim 24

The balanced differential input circuit of claim 17 wherein the emitter impedance includes a first resistor.

Claim 25

The balanced differential input circuit of claim 17 including another resistor and a capacitor connected in series between the terminals of the emitter impedance terminals to provide high-frequency boost for the input circuit.

Claim 26

The balanced differential input circuit of claim 17 wherein the first and the second NPN transistors are formed as a composite transistor with two emitter regions, one collector region, and one base region and wherein the third and fourth NPN transistors are also formed as a composite transistor with two emitter regions, one collector region, and one base region.