Patent US6103135A successfully refreshed from Google Patents.
Patent US5514905A successfully refreshed from Google Patents.
US5514905A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Hitachi Ltd
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Filing: 1994-10-27
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Granted: 1996-05-07
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Expires: 2014-10-27
Abstract
Abstract A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
Inventors
- 👤 Toshiyuki Sakuta
- 👤 Kazuyuki Miyazawa
- 👤 Satoshi Oguchi
- 👤 Aizo Kaneda
- 👤 Masao Mitani
- 👤 Shozo Nakamura
- 👤 Kunihiko Nishi
- 👤 Gen Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:05
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W74/00; H10W74/40; H10W74/47; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/90; H10W72/951; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
217 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface, and said plurality of leads being electrically connected to said plurality of electrodes, respectively; and a resin for molding said semiconductor chip and the inner lead portions of said plurality of leads.
Claim 2
Dependent Claim
217 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface, and said plurality of leads being electrically connected to said plurality of electrodes, respectively; and a resin for molding said semiconductor chip and the inner lead portions of said plurality of leads.
Claim 3
Dependent Claim
23 words
A semiconductor memory device according to claim 1, wherein said plurality of leads are electrically connected to said electrodes by bonding wires, respectively.
Claim 4
Dependent Claim
18 words
A semiconductor memory device according to claim 1, wherein said plurality of electrodes are arranged in two rows.
Claim 5
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 6
Dependent Claim
23 words
A semiconductor memory device according to claim 3, wherein said plurality of leads are electrically connected to said electrodes by bonding wires, respectively.
Claim 7
Dependent Claim
50 words
A semiconductor memory device according to claim 5, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 8
Dependent Claim
50 words
A semiconductor memory device according to claim 3, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 9
Dependent Claim
228 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface; means for electrically connecting the end portions of said plurality of leads with associated ones of said plurality of electrodes, respectively; and a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and the electrically connecting means.
Claim 10
Dependent Claim
228 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface; means for electrically connecting the end portions of said plurality of leads with associated ones of said plurality of electrodes, respectively; and a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and the electrically connecting means.
Claim 11
Dependent Claim
16 words
A semiconductor memory device according to claim 8, wherein said electrically connecting means consist of wires.
Claim 12
Dependent Claim
18 words
A semiconductor memory device according to claim 8, wherein said plurality of electrodes are arranged in two rows.
Claim 13
Dependent Claim
50 words
A semiconductor memory device according to claim 8, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 14
Dependent Claim
16 words
A semiconductor memory device according to claim 10, wherein said electrically connecting means consist of wires.
Claim 15
Dependent Claim
50 words
A semiconductor memory device according to claim 12, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 16
Dependent Claim
50 words
A semiconductor memory device according to claim 10, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 17
Dependent Claim
238 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of bonding pads arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed bonding pads so that the arrayed bonding pads are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed bonding pads, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed bonding pads; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface, a plurality of wires each of which electrically connecting said end portion of a respective lead with an associated one of said plurality of bonding pads; and a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said plurality of wires.
Claim 18
Dependent Claim
238 words
A semiconductor memory device comprising: a rectangular-shaped semiconductor chip having a main surface; a plurality of bonding pads arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row; first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed bonding pads so that the arrayed bonding pads are interposed between said first and second memory cell array regions; first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed bonding pads, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed bonding pads; a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface, a plurality of wires each of which electrically connecting said end portion of a respective lead with an associated one of said plurality of bonding pads; and a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said plurality of wires.
Claim 19
Dependent Claim
19 words
A semiconductor memory device according to claim 15, wherein said plurality of bonding pads are arranged in two rows.
Claim 20
Dependent Claim
50 words
A semiconductor memory device according to claim 15, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
Claim 21
Dependent Claim
50 words
A semiconductor memory device according to claim 16, wherein said semiconductor chip has an elongated rectangular shape which is comprised of a pair of longer edges and a pair of shorter edges, and wherein said plurality of leads extend outwardly via said pair of longer edges of said semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |