Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset

Claim 2

In a computer system comprising a processor, an address decoder, and a system bus having a plurality of connector slots, wherein the processor and the address decoder are both coupled to the bus; and one or more memory units are correspondingly connected to one or more of the connector slots, a method for automatically configuring system memory address space of the computer system during system reset, the method comprising the steps of: (a) concurrently outputting and maintaining one or more memory sizes of the one or more memory units on one or more groups of private bus signal lines of the system bus, through the connector slot(s), by the one or more memory units, while system reset is in progress, responsive to a system reset bus signal so denoting; (b) concurrently coupling the memory size(s) maintained by the memory unit(s) on the private bus signal lines to the address decoder by the bus while the memory size(s) are being output and maintained; and (c) systematically reading the private bus signal lines, one group of private bus signal line(s) at a time, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signals, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 3

A computer system comprising: a processor; one or more memory units including one or more first circuitry correspondingly disposed on the one or more memory units for outputting memory size(s) and maintaining the output(s) while system reset is in progress, responsive to a system reset bus signal so denoting; a system bus coupled to the processor, the system bus having a plurality of connector slots against which the memory unit(s) are connected, and multiple groups of private bus signal lines correspondingly coupled to the connector signals, for concurrently transporting the memory size(s) output by the memory unit(s); as address decoder for systematically reading the private bus signal lines, one group of private bus signal line(s) at a time, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 4

A computer system comprising: a processor; one or more memory units including one or more first circuitry correspondingly disposed on the one or more memory units for outputting memory size(s) and maintaining the output(s) while system reset is in progress, responsive to a system reset bus signal so denoting; a system bus coupled to the processor, the system bus having a plurality of connector slots against which the memory unit(s) are connected, and multiple groups of private bus signal lines correspondingly coupled to the connector signals, for concurrently transporting the memory size(s) output by the memory unit(s); as address decoder for systematically reading the private bus signal lines, one group of private bus signal line(s) at a time, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 5

In a computer system comprising a processor, an address decoder, and a system bus having a plurality of connector slots, wherein the processor and the address decoder are both coupled to the bus, and one or more memory units are correspondingly connected to one or more of the connector slots, a method for automatically configuring system memory address space of the computer system during system reset, the method comprising the steps of: (a) outputting and maintaining one memory size of a selected one of the one or more memory units on one or more shared bus signal lines of the system bus, through one of the connector slot(s), by the selected one of the one or more memory units, while system reset is in progress, responsive to a system reset bus signal so denoting; (b) coupling the memory size maintained by the selected memory unit on the shared bus signal lines to the address decoder by the bus while the memory size is being output and maintained; and (c) systematically selecting the memory unit(s) and reading the shared bus signal lines, one memory unit at a time, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 6

In a computer system comprising a processor, an address decoder, and a system bus having a plurality of connector slots, wherein the processor and the address decoder are both coupled to the bus, and one or more memory units are correspondingly connected to one or more of the connector slots, a method for automatically configuring system memory address space of the computer system during system reset, the method comprising the steps of: (a) outputting and maintaining one memory size of a selected one of the one or more memory units on one or more shared bus signal lines of the system bus, through one of the connector slot(s), by the selected one of the one or more memory units, while system reset is in progress, responsive to a system reset bus signal so denoting; (b) coupling the memory size maintained by the selected memory unit on the shared bus signal lines to the address decoder by the bus while the memory size is being output and maintained; and (c) systematically selecting the memory unit(s) and reading the shared bus signal lines, one memory unit at a time, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 7

A computer system comprising: a processor; one or more memory units including one or more first circuitry correspondingly disposed on the one or more memory units for outputting memory size(s) in turn, responsive to a plurality of selection signal denoting when each memory is selected for output, and maintaining each output during each memory unit's turn, while system reset is in progress, responsive to a system reset bus signal so denoting: a system bus coupled to the processor, the system bus having a plurality of connector slots against which the memory unit(s) are connected, and one or more shared bus signal lines coupled to the connector slots, for transporting the memory size output by the selected memory unit; as address decoder for systematically selecting the one or more memory units, one memory unit at a time, reading the shared bus signal lines, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.

Claim 8

A computer system comprising: a processor; one or more memory units including one or more first circuitry correspondingly disposed on the one or more memory units for outputting memory size(s) in turn, responsive to a plurality of selection signal denoting when each memory is selected for output, and maintaining each output during each memory unit's turn, while system reset is in progress, responsive to a system reset bus signal so denoting: a system bus coupled to the processor, the system bus having a plurality of connector slots against which the memory unit(s) are connected, and one or more shared bus signal lines coupled to the connector slots, for transporting the memory size output by the selected memory unit; as address decoder for systematically selecting the one or more memory units, one memory unit at a time, reading the shared bus signal lines, incrementally configuring the system address space in accordance to the memory size(s) systematically read, and retaining the system address space configuration information by the address decoder, while system reset is in progress, responsive to the same system reset bus signal, the retained system address configuration information being used by the address decoder subsequently during operation to select the appropriate ones of the one or more memory units when the one or more memory units are address by the processor.