EP0285986A2
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EP
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Data processing system with means for contiguously addressing memory
Assignee: International Business Machines Corp
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Filing: 1988-03-29
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Granted: —
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Expires: 2008-03-29
Abstract
Abstract A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.
Inventors
- 👤 Dag Reidar Blokkum
- 👤 Charles Ray Johns
- 👤 Lee Jack Morozink
- 👤 David Lawrence Peterson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 11:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0684
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
203 words
A digital data processing system including a memory address bus (18) and an addressing system (12) for addressing a memory means (14A - 14D) in response to signals on said address bus, said memory means comprising a plurality of memory receiving banks each for holding up to a predetermined fixed capacity of memory, characterised by means (30) associated with the banks for generating capacity signals indicating the capacity, including zero, of memory currently held in each bank, and in that said addressing system includes means (32, 34), responsive to the indications of the capacity and to address signals on said address bus for contiguously addressing the memory currently held in the banks, said means responsive comprising a plurality of logic cells coupled to receive segment signals derived from high order address bits from said address bus signals and representing consecutive fixed sized segments of the memory together with said capacity signals, said logic cells being intercoupled to provide, in response to said capacity signals and said segment signals, signals for selecting the memory banks to provide, in combination with low order address bits on the address bus, contiguous addresses for the memory irrespective of the capacity of memory in each of said banks.
Claim 2
Dependent Claim
203 words
A digital data processing system including a memory address bus (18) and an addressing system (12) for addressing a memory means (14A - 14D) in response to signals on said address bus, said memory means comprising a plurality of memory receiving banks each for holding up to a predetermined fixed capacity of memory, characterised by means (30) associated with the banks for generating capacity signals indicating the capacity, including zero, of memory currently held in each bank, and in that said addressing system includes means (32, 34), responsive to the indications of the capacity and to address signals on said address bus for contiguously addressing the memory currently held in the banks, said means responsive comprising a plurality of logic cells coupled to receive segment signals derived from high order address bits from said address bus signals and representing consecutive fixed sized segments of the memory together with said capacity signals, said logic cells being intercoupled to provide, in response to said capacity signals and said segment signals, signals for selecting the memory banks to provide, in combination with low order address bits on the address bus, contiguous addresses for the memory irrespective of the capacity of memory in each of said banks.
Claim 3
Dependent Claim
77 words
A digital data processing system according to claim 1, including a segment signal generator comprising a translator receiving the N highest order address bits from said address bus (where N is a positive integer greater than 1), and having 2 to the power N output lines, each energised by a different unique combination of the N high order address bits to carry said segment signals, whereby each segment signal represents a fixed sized range of memory addresses.
Claim 4
Dependent Claim
94 words
A digital data processing system according to claim 1 or claim 2, in which there are P banks of memory, each said predetermined fixed maximum memory capacity of each memory bank comprises a fixed number, 1 of said segments of memory 1 where 1 and P are integers greater than 1), and said logic cells are arranged in a matrix of P columns and 1/P rows, each row receiving 1 consecutive segment signals, with adjacent rows receiving consecutive groups of the segment signals, and each column receiving said capacity signals form corresponding memory banks.
Claim 5
Dependent Claim
84 words
A digital data processing system according to claim 4, in which each row of the matrix is arranged to pass each segment signal logically along the row to provide a corresponding output segment signal when each prior segment corresponding to lower ordered addresses of the memory has been allocated to a memory bank containing memory as indicated by the capacity signals, said output segment signals being operable to address memory within a bank in conjunction with low order address bit from said address bus.
Claim 6
Dependent Claim
75 words
A digital data processing system according to claim 3 or claim 4, in which each column of the matrix is arranged to direct the capacity signals logically through each logic cell in the column to control selection of said segment signals for addressing the memory, and, when the capacity signals indicate a capacity greater than zero in the corresponding memory bank, to generate a bank select signal for selecting the bank for memory access therein.
Claim 7
Dependent Claim
44 words
A digital data processing system according to any one of claims 3 to 5, in which the logic cells in the columns comprise from 1 to P, increasing by one for each consecutive column corresponding to memory banks containing consecutively higher orders of addresses.
Claim 8
Dependent Claim
47 words
A digital data processing system according to any one of claims 3 to 6, in which the logic cells in the rows comprise from P to 1, decreasing by one for each set of segment signals corresponding to memory segments with consecutively higher ordered memory addresses therein.
Claim 9
Dependent Claim
43 words
A digital data processing system according to any of the previous claims, in which said memory is a dynamic random access memory, and said logic cells provide signals controlling different Row Address Select and Column Address Select signals to access different memory areas.
Claim 10
Independent Claim
101 words
A method of addressing a memory in a digital data processing system, said memory having a plurality of memory banks for holding memory modules of up to a fixed maximum size, and having associated with each bank means for developing size signals indicating the size of memory currently therein, and said system including segment lines energisable to define associated fixed sized segments of memory, comprising the steps of, logically processing signals on said segment lines in response to said size signals for generating output segment signals corresponding in number to, and location with, the memory modules currently held in said banks.
Claim 11
Independent Claim
101 words
A method of addressing a memory in a digital data processing system, said memory having a plurality of memory banks for holding memory modules of up to a fixed maximum size, and having associated with each bank means for developing size signals indicating the size of memory currently therein, and said system including segment lines energisable to define associated fixed sized segments of memory, comprising the steps of, logically processing signals on said segment lines in response to said size signals for generating output segment signals corresponding in number to, and location with, the memory modules currently held in said banks.
References Cited (Backward Citations)
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