Low-voltage cascaded current mirror circuit with improved power supply rejection and method therefor

Claim 2

A circuit comprising: a current source providing an input current (I1); a first current mirror circuit coupled to said current source, said first current mirror circuit having an output current (I2); an error current generator coupled to said first current mirror circuit, said error current generator generating at an output an error current (I eer ) representative of the difference between an expected value of said input current (I1) and an actual value thereof; a second current mirror circuit coupled to said output of said error current generator for replicating said error current (I err ); and a summing circuit coupled to said error current generator and said second current mirror circuit, said summing circuit generating at an output a current substantially equal to said input current (I1), or a designed multiple thereof.

Claim 3

The circuit of claim 1 wherein said error current generator comprises: a third current mirror circuit coupled to said first current mirror circuit, said third current mirror circuit having an output current (I3) at an output; and an input current replicator coupled to said output of said third current mirror circuit, wherein, said input current replicator subtracts an amount of current substantially equal to said input current (I1) from said output current of said third Current mirror circuit (I3) to generate said error current (I eer ).

Claim 4

A circuit comprising: a current source for providing an input current (I1); a first pair of transistors having common control terminals and forming a first current mirror circuit with an input coupled to said current source, said first current mirror circuit generating a first mirror current (I2) at an output; a second pair of transistors having common control terminals and forming a second current mirror circuit with an input coupled to said first current mirror circuit output, said second current mirror circuit generating a second mirror current (I3) at an output; a first mirror transistor having a control terminal coupled to said control terminals of said first pair of transistors, and an output coupled to said output of said second pair of transistors; a third pair of transistors having common control terminals and forming a third current mirror circuit with an input coupled to said second current mirror circuit output, said third current mirror circuit generating an error current I err at an output; and a second mirror transistor having a control terminal coupled to said control terminals of said second pair of transistors, and an output coupled to said output of said third pair of transistors.

Claim 5

A circuit comprising: a current source for providing an input current (I1); a first pair of transistors having common control terminals and forming a first current mirror circuit with an input coupled to said current source, said first current mirror circuit generating a first mirror current (I2) at an output; a second pair of transistors having common control terminals and forming a second current mirror circuit with an input coupled to said first current mirror circuit output, said second current mirror circuit generating a second mirror current (I3) at an output; a first mirror transistor having a control terminal coupled to said control terminals of said first pair of transistors, and an output coupled to said output of said second pair of transistors; a third pair of transistors having common control terminals and forming a third current mirror circuit with an input coupled to said second current mirror circuit output, said third current mirror circuit generating an error current I err at an output; and a second mirror transistor having a control terminal coupled to said control terminals of said second pair of transistors, and an output coupled to said output of said third pair of transistors.

Claim 6

The circuit of claim 3 wherein said first, second and third pairs of transistors in said first, second and third current mirror circuits have a first input diode-coupled transistor and a second output transistor.

Claim 7

The circuit of claim 4 wherein all transistors are bipolar transistors.

Claim 8

The circuit of claim 4 wherein all transistors are field effect transistors.

Claim 9

The circuit of claim 4 wherein said pairs of transistors and mirror transistors are selectively implemented in field effect transistor technology and bipolar transistor technology.

Claim 10

The circuit of claim 4 wherein some current mirrors comprise bipolar transistors and others comprise field-effect transistors.

Claim 11

The circuit of claim 4 wherein each of said current mirror circuits further comprises: an emitter-follower transistor to connect a base and a collector of said diode-coupled transistor; and a resistor coupled between said common base terminals and a power supply terminal or ground.