Semiconductor chip packages

Claim 2

A semiconductor chip package comprising: a chip package having at least one semiconductor chip disposed therein; and a plurality of first and second pins extending from the package, each first pin being electrically connected to the at least one semiconductor chip to conduct signals between said at least one semiconductor chip and circuitry external to the chip package and each second pin being redundant and not electrically connected to the at least one semiconductor chip, the first pins comprising a plurality of groups which includes a first group and more than one remaining group, each said group consisting of one or more pins and being arranged to conduct a respective signal type, there being at least one pair of first group and second pins, the respective pins of each said pair being functionally asymmetrically disposed in opposed relation along respective opposite or adjacent edges of the package, each said remaining group of first pins being mutually symmetrically disposed along opposite or adjacent edges of the package.

Claim 3

A semiconductor chip package according to claim 1 wherein the first and second pins are located on a pair of opposed edges of the package.

Claim 4

A semiconductor chip package according to claim 2 wherein the symmetrical disposition of the said remaining groups of first pins is reflective symmetry.

Claim 5

A semiconductor chip package according to claim 2 wherein each first pin of the said remaining groups is opposite to a respective first pin of the same group and each first group pin is opposite a respective second pin.

Claim 6

A semiconductor chip package according to claim 3 wherein each first pin of the said remaining groups is opposite to a respective first pin of the same group and each first group pin is opposite a respective second pin.

Claim 7

A semiconductor chip package according to claim 1 wherein the first group pins comprise chip select pins.

Claim 8

A semiconductor chip package according to claim 1 wherein the first group pins comprise data pins.

Claim 9

A semiconductor chip package according to claim 1 wherein the first and second pins are located on each of four edges of the package.

Claim 10

A semiconductor chip package according to claim 8 wherein the symmetrical disposition of the said remaining groups of first pins on opposed edges of the package is reflective symmetry.

Claim 11

A semiconductor chip package according to claim 8 wherein the symmetrical disposition of the said remaining groups of first pins on adjacent edges of the package is rotational symmetry.

Claim 12

A semiconductor chip package according to claim 8 wherein the said first group pins and the second pins are asymmetrically disposed on the opposed edges of the package.

Claim 13

A semiconductor chip package according to claim 8 wherein each first pin of the said remaining group is opposite a respective second pin, and each second pin which is not opposite a respective first group pin is opposite a respective second pin.

Claim 14

A semiconductor chip package according to claim 8 wherein the first group pins comprise chip select pins.

Claim 15

A semiconductor chip package according to claim 8 wherein the first group pins comprises data pins.

Claim 16

A module of semiconductor chip packages, the module comprising two semiconductor chip packages according to claim 1 which are stacked together to form a stacked pair of packages with each first pin of the said remaining groups of one package being connected to a corresponding first pin of the other package and each first group pin of the said one package being connected to a respective second pin of the said other package.

Claim 17

A module according to claim 15 wherein the said other package is mounted upside-down on the said one package and the said first and second pins of the two packages are connected along common edges of the module.

Claim 18

A module according to claim 16 wherein in each package the first and second pins are located on each of four edges of the package, and further comprising an additional stacked pair of packages which is stacked above the first-mentioned stacked pair, the additional stacked pair being rotated relative to the first stacked pair with each first pin/first pin connection of the first stacked pair being connected to a first pin/first pin connection of the additional stacked pair and each first pin/second pin connection of the first stacked pair being connected to a second pin/second pin connection of the additional stacked pair.

Claim 19

A module according to claim 17 further comprising two further stacked pairs of packages which are stacked above the said additional stacked pair, the two further stacked pairs being rotated relative to each other and relative to each of the first-mentioned and additional stacked pairs.

Claim 20

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising: a package for containing one or more integrated circuit chips; integrated circuitry comprising one or more integrated circuits located within the package; the package having first, second, third and fourth sides; an imaginary first axis of symmetry located between the first and third sides; first, second and third groups of pins located symmetrically on said package, said third group consisting of at least one pin; said first group of pins being electrically coupled to said integrated circuitry in the package, said first group of pins being located on said first and third sides of the package; said second group of pins not being electrically coupled to the integrated circuitry in the package, said second group of pins being located on said first side of the package; said third group of pins being electrically coupled to the integrated circuitry in the package, said third group of pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said second pins, with respect to said imaginary axis, so that said third pins are located opposite to said second pins; said first group of pins being organized into and comprising two or more sets of pins, each respective set of said first group of pins having two or more pins; said integrated circuit being coupled to receive at least two types of signals; each said set in said first group of pins being identified with and coupled to conduct a corresponding one of said types of signals to be received by said integrated circuitry; within said first group of pins, any two or more power supply pins forming a first set, any two or more data pins forming a second set, any two or more address pins forming a third set; and any two or more ground pins forming a fourth set; each set of said first group of pins comprising pins that are located on both said first and third sides of said package at locations that are reflectively symmetric about said imaginary axis, whereby the pins of the first set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis, and the pins of the second set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis; the first group of pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first group of pins of one said package is aligned over said first group of pins of the other package; the third group of pins being positioned so that when said integrated circuit package is so stacked, at least one pin of the third group of pins of one package is aligned with at least one pin of the second group of pins of the other package; whereby the relative configuration of the first, second and third groups of pins allows identical integrated circuit packages to be stacked and functionally interconnected.

Claim 21

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising: a package for containing one or more integrated circuit chips; integrated circuitry comprising one or more integrated circuits located within the package; the package having first, second, third and fourth sides; an imaginary first axis of symmetry located between the first and third sides; first, second and third groups of pins located symmetrically on said package, said third group consisting of at least one pin; said first group of pins being electrically coupled to said integrated circuitry in the package, said first group of pins being located on said first and third sides of the package; said second group of pins not being electrically coupled to the integrated circuitry in the package, said second group of pins being located on said first side of the package; said third group of pins being electrically coupled to the integrated circuitry in the package, said third group of pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said second pins, with respect to said imaginary axis, so that said third pins are located opposite to said second pins; said first group of pins being organized into and comprising two or more sets of pins, each respective set of said first group of pins having two or more pins; said integrated circuit being coupled to receive at least two types of signals; each said set in said first group of pins being identified with and coupled to conduct a corresponding one of said types of signals to be received by said integrated circuitry; within said first group of pins, any two or more power supply pins forming a first set, any two or more data pins forming a second set, any two or more address pins forming a third set; and any two or more ground pins forming a fourth set; each set of said first group of pins comprising pins that are located on both said first and third sides of said package at locations that are reflectively symmetric about said imaginary axis, whereby the pins of the first set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis, and the pins of the second set are located on the first and third sides of the package at locations that are reflectively symmetric to each other with respect to the imaginary axis; the first group of pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first group of pins of one said package is aligned over said first group of pins of the other package; the third group of pins being positioned so that when said integrated circuit package is so stacked, at least one pin of the third group of pins of one package is aligned with at least one pin of the second group of pins of the other package; whereby the relative configuration of the first, second and third groups of pins allows identical integrated circuit packages to be stacked and functionally interconnected.

Claim 22

A package according to claim 19 wherein said package is stackable with another identical package to form a stacked module and wherein in said stacked module said remaining groups of said first pins are aligned over said remaining groups of said first pins of said other identical package, and said chip select signal group of said package is aligned with said second pins of said other identical package.

Claim 23

A package according to claim 1 wherein said semiconductor chip is a semiconductor memory chip.

Claim 24

A package according to claim 21 wherein the first pins of the said at least one group comprise chip select pins and the first pins of the remaining groups comprise voltage, ground, address, data, write enable and output enable pins.

Claim 25

A semiconductor chip package comprising: a chip package; at least one semiconductor chip disposed in said package; a plurality of pins disposed on the package, the pins comprising pairs of matching first pins connected to circuitry in the package for conducting first types of signals, the pins of each pair being arranged to conduct respective signals having a similar function; at least one second pin disposed on and connected to circuitry in the package for conducting signals of a second type, the semiconductor chip package being responsive to one or more of said signals of a second type; and at least one third pin disposed on the package, the at least one third pin being a redundant pin which is not connected to circuitry in the package; the distribution of the first, second and third pins being such that first and second packages may be located adjacent each other with each first pin on the first package connecting with a matching first pin on the second package and with said at least one second pin on the first package connecting with said at least one third pin on the second package.

Claim 26

A semiconductor chip package comprising: a chip package; at least one semiconductor chip disposed in said package; a plurality of pins disposed on the package, the pins comprising pairs of matching first pins connected to circuitry in the package for conducting first types of signals, the pins of each pair being arranged to conduct respective signals having a similar function; at least one second pin disposed on and connected to circuitry in the package for conducting signals of a second type, the semiconductor chip package being responsive to one or more of said signals of a second type; and at least one third pin disposed on the package, the at least one third pin being a redundant pin which is not connected to circuitry in the package; the distribution of the first, second and third pins being such that first and second packages may be located adjacent each other with each first pin on the first package connecting with a matching first pin on the second package and with said at least one second pin on the first package connecting with said at least one third pin on the second package.

Claim 27

A semiconductor chip package according to claim 23 wherein said first, second and third pins are located on a pair of opposed edges of the package.

Claim 28

A semiconductor chip package according to claim 23 wherein each part of matching first pins is disposed in opposed relation on the pair of opposed edges of the package and each second pin is opposite a respective third pin.

Claim 29

A semiconductor chip package according to claim 23 wherein the first, second and third pins are located on each of four edges of the package.

Claim 30

A semiconductor chip package according to claim 26 wherein each pair of matching first pins is disposed in opposed relation on an opposed pair of the four edges of the package.

Claim 31

A semiconductor chip package according to claim 26 wherein each second pin is opposite a respective third pin, and each third pin which is not opposite a respective second pin is opposite a respective third pin.

Claim 32

A semiconductor chip package according to claim 23 wherein the second pins comprise chip select pins.

Claim 33

A semiconductor chip package according to claim 23 wherein the second pins comprise data pins.

Claim 34

A semiconductor chip package according to claim 23 wherein the first pins comprise voltage, ground, address, data, write enable and output enable pins.

Claim 35

A semiconductor chip package according to claim 23, wherein the semiconductor chip is a semiconductor memory chip.

Claim 36

A module of semiconductor chip packages, the module comprising two semiconductor chip packages according to claim 23 which are stacked together to form a stacked pair of packages with each first pin of one package being connected to a matching first pin of the other package and each second pin of tile said one package being connected to a respective third pin of tile said other package.

Claim 37

A module according to claim 33 wherein tile said other package is mounted upside-down on the said one package and the first, second and third pins of the two packages are connected along common edges of tile module.

Claim 38

A module according to claim 33 wherein in each package the first, second and third pins are located on each of four edges of the package, and further comprising an additional stacked pair of packages which is stacked above the first-mentioned stacked pair, the additional stacked pair being rotated relative to tile first stacked pair with each first pin/first pin connection of the first stacked pair being connected to a matching first pin/first pin connection of the additional stacked pair and each second pin/third pin connection of the first stacked pair being connected to a third pin/third pin connection of the additional stacked pair.

Claim 39

A module according to claim 34 further comprising two further stacked pairs of packages which are stacked above the said additional smoked pair, the two further stacked pairs being rotated relative to each other and relative to each of the first-mentioned and additional stacked pairs.

Claim 40

A semiconductor chip package according to claim 23 wherein said package has an axis of symmetry for the location of first pins, two pins of a matching pair of first pins being located symmetrically relative to each other with respect to said axis, whereby each may be located against a matching pin on an adjacent package, and said at least one second pin is located symmetrically with respect to said axis with said at least one third pin.

Claim 41

A semiconductor chip package according to claim 37 wherein said first, second and third pins are located on a pair of opposed edges of the package.

Claim 42

A semiconductor chip package according to claim 37 wherein each pair of matching first pins is disposed in opposed relation on the pair of opposed edges of the package and each second pin is opposite a respective third pin.

Claim 43

A semiconductor chip package according to claim 37 wherein the first, second and third pins are located on each of four edges of the package.

Claim 44

A semiconductor chip package according to claim 40 wherein each pair of matching first pins is disposed in opposed relation on an opposed pair of the four edges of the package.

Claim 45

A semiconductor chip package according to claim 39 wherein each second pin is opposite a respective third pin, and each third pin which is not opposite a respective second pin is opposite a respective third pin.

Claim 46

A semiconductor chip package according to claim 37 wherein the second pins comprise chip select pins.

Claim 47

A semiconductor chip package according to claim 37 wherein the second pins comprise data pins.

Claim 48

A semiconductor chip package according to claim 37 wherein the first pins comprise voltage, ground, address, data, write enable and output enable pins.

Claim 49

A semiconductor chip package according to claim 37, wherein the semiconductor chip is a semiconductor memory chip.

Claim 50

A module of semiconductor chip packages, the module comprising two semiconductor chip packages according to claim 36 which are stacked together to form a stacked pair of packages with each first pin of one package being connected to a matching first pin of the other package and each second pin of the said one package being connected to a respective third pin of the said other package.

Claim 51

A module according to claim 47 wherein the said other package is mounted upside-down on the said one package and the first, second and third pins of the two packages are connected along common edges of the module.

Claim 52

A module according to claim 47 wherein in each package the first, second and third pins are located on each of four edges of the package, and further comprising an additional stacked pair of packages which is stacked above the first mentioned stacked pair, the additional stacked pair being rotated relative to the first stacked pair with each first pin/first pin connection of the first stacked pair being connected to a matching first pin/first pin connection of the additional stacked pair and each second pin/third pin connection of the first stacked part being connected to a third pin/third pin connection of the additional stacked pair.

Claim 53

A module according to claim 48 further comprising two further stacked pairs of packages which are stacked above the said additional stacked pair, the two further stacked pairs being rotated relative to each other and relative to each of the first-mentioned and additional stacked pairs.

Claim 54

A semiconductor chip package according to claim 23, wherein the signals of the second type are arranged to select at least part of the package so as to render operative at least some of the first pins of the package.

Claim 55

A semiconductor chip package according to claim 51, wherein when the first and second packages are located adjacent each other, each pin on each package is connected with a respective pin on the other package.

Claim 56

A semiconductor chip package according to claim 37, wherein the signals of the second type are arranged to select at least part of the package so as to render operative at least some of the first pins of the package.

Claim 57

A semiconductor chip package according to claim 53, wherein each pin on each package is connected with a respective pin on the other package when tile first and second packages are located adjacent each other, each pin on each package is connected with a respective pin on the other package.

Claim 58

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising: a chip package; an integrated circuit located within the package; the package having first, second, third and fourth sides; an imaginary first axis of symmetry located between the first and third sides; a plurality of pins located symmetrically on said package, including first pins connected to the integrated circuit within the package for receiving and supplying address signals, data signals, power supply signals, and a ground signal; the pins for supplying the address signals being symmetrically located about said axis; the pins for supplying the data signals being symmetrically located about said axis; the pins for supplying the power supply signals being symmetrically located about said axis; the pins for supplying the ground signals being symmetrically located about said axis; said plurality of pins including one or more unconnected pins which are not electrically coupled to the integrated circuit in the package, said unconnected pins being located on said first side of the package; said plurality of pins including one or more chip enable pins electrically coupled to the integrated circuit in the package, said chip enable pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said unconnected pins, with respect to said imaginary axis, so that said chip enable pins are located opposite to said unconnected pins; the first pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first pins of one said package are aligned over said first pins of the other package; the chip enable pins being positioned so that when said packages are stacked, at least one of the chip enable pins of one package is aligned with at least one unconnected pin of the other package; whereby the relative configuration of the pins allows identical integrated circuit packages to be stacked and functionally interconnected.

Claim 59

A package for one or more integrated circuits contained therein, the package being adapted for stacking with identical ones of such packages, comprising: a chip package; an integrated circuit located within the package; the package having first, second, third and fourth sides; an imaginary first axis of symmetry located between the first and third sides; a plurality of pins located symmetrically on said package, including first pins connected to the integrated circuit within the package for receiving and supplying address signals, data signals, power supply signals, and a ground signal; the pins for supplying the address signals being symmetrically located about said axis; the pins for supplying the data signals being symmetrically located about said axis; the pins for supplying the power supply signals being symmetrically located about said axis; the pins for supplying the ground signals being symmetrically located about said axis; said plurality of pins including one or more unconnected pins which are not electrically coupled to the integrated circuit in the package, said unconnected pins being located on said first side of the package; said plurality of pins including one or more chip enable pins electrically coupled to the integrated circuit in the package, said chip enable pins being located on said third side of the package and disposed at a location that is reflectively symmetric to said unconnected pins, with respect to said imaginary axis, so that said chip enable pins are located opposite to said unconnected pins; the first pins being positioned so that when a said integrated circuit package is stacked with another like integrated circuit package, the first pins of one said package are aligned over said first pins of the other package; the chip enable pins being positioned so that when said packages are stacked, at least one of the chip enable pins of one package is aligned with at least one unconnected pin of the other package; whereby the relative configuration of the pins allows identical integrated circuit packages to be stacked and functionally interconnected.

Claim 60

A module of at least two identical semiconductor chip packages, each said package including at least one respective semiconductor chip disposed therein and a respective array of pins disposed on the package, each said array of pins including connected pins which are connected to the at least one semiconductor chip in the respective package and further including at least one redundant pin, the packages being stacked and electrically connected together to form the module, the pins of each array connecting with the pins of the or each array adjacent thereto thereby to form a composite array of module connections, a plurality of first module connections being comprised of connected pins, the connected pins of each first module connection being arranged to conduct a signal of a common function type, and at least two second module connections being comprised of one connected pin and at least one redundant pin, each second module connection being arranged to conduct via the respective connected pin thereof a signal to that package of the stack which comprises the said respective connected pin.

Claim 61

A module of at least two identical semiconductor chip packages, each said package including at least one respective semiconductor chip disposed therein and a respective array of pins disposed on the package, each said array of pins including connected pins which are connected to the at least one semiconductor chip in the respective package and further including at least one redundant pin, the packages being stacked and electrically connected together to form the module, the pins of each array connecting with the pins of the or each array adjacent thereto thereby to form a composite array of module connections, a plurality of first module connections being comprised of connected pins, the connected pins of each first module connection being arranged to conduct a signal of a common function type, and at least two second module connections being comprised of one connected pin and at least one redundant pin, each second module connection being arranged to conduct via the respective connected pin thereof a signal to that package of the stack which comprises the said respective connected pin.

Claim 62

A module according to claim 56 wherein at least one second module connection is assigned to conduct a chip select signal.

Claim 63

A module according to claim 56 wherein at least one each second module connection is assigned to conduct a data signal.

Claim 64

A module according to claim 56, wherein each package in the stack has a respective unique orientation in the stack.

Claim 65

A module according to claim 56, wherein each package in the stack has an orientation which is at least one of a rotated orientation and an inverted orientation relative to an orientation of the or each adjacent package in the stack.