Level translator with a voltage shifting element

Claim 2

A level translator, comprising: a source of a switching, first input voltage; a first transistor responsive to said first switching input voltage for performing a switching operation; a pair of second and third transistors cross-coupled to each other to form a latch; a first level shifter for level shifting in a first direction a voltage developed in said first transistor and for applying the level shifted voltage to a terminal of said latch to establish said latch at a first state when said first input voltage is at a first state, such that when said first input voltage is at a second state, said input voltage causes said latch to be at a second state, said level shifter level shifting in an opposite direction a voltage that is developed at said terminal of said latch and applying the level shifted latch voltage to said first transistor, when said latch is at said second state, said level shifter level shifting in one of said directions in steady state operation; and an output fourth transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a level of said first input voltage when said latch is at one of said first and second states.

Claim 3

A level translator according to claim 1 wherein said level shifted voltage that is applied to said latch by said first level shifter protects one of said transistors of said latch against an over-voltage condition and said level shifted latch voltage protects said first transistor against an over-voltage condition in said first transistor.

Claim 4

A level translator comprising: a source of a switching, first input voltage; a first transistor responsive to said first switching input voltage for performing a switching operation; a pair of second and third transistors cross-coupled to each other to form a latch; a first level shifter for level shifting in a first direction a voltage developed in said first transistor and for applying the level shifted voltage to a terminal of said latch to establish said latch at a first state when said first input voltage is at a first state, such that when said first input voltage is at a second state, said input voltage causes said latch to be at a second state, said level shifter level shifting in an opposite direction a voltage that is developed at said terminal of said latch and applying the level shifted latch voltage to said first transistor, when said latch is at said second state wherein said first level shifter comprises a diode that is coupled in series with said first transistor and with one of said second and third transistors; and an output fourth transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a level of said first input voltage when said latch is at one of said first and second states.

Claim 5

A level translator comprising: a source of a switching, first input voltage; a first transistor responsive to said first switching input voltage for performing a switching operation; a pair of second and third transistors cross-coupled to each other to form a latch; a first level shifter for level shifting in a first direction a voltage developed in said first transistor and for applying the level shifted voltage to a terminal of said latch to establish said latch at a first state when said first input voltage is at a first state, such that when said first input voltage is at a second state, said input voltage causes said latch to be at a second state, said level shifter level shifting in an opposite direction a voltage that is developed at said terminal of said latch and applying the level shifted latch voltage to said first transistor, when said latch is at said second state wherein said first level shifter comprises a diode that is coupled in series with said first transistor and with one of said second and third transistors; and an output fourth transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a level of said first input voltage when said latch is at one of said first and second states.

Claim 6

A level translator, comprising: a source of a switching, first input voltage; a first transistor responsive to said first switching input voltage for performing a switching operation; a pair of second and third transistors cross-coupled to each other to form a latch; a first level shifter for level shifting in a first direction a voltage developed in said first transistor and for applying the level shifted voltage to a terminal of said latch to establish said latch at a first state when said first input voltage is at a first state, such that when said first input voltage is at a second state, said input voltage causes said latch to be at a second state, said level shifter level shifting in an opposite direction a voltage that is developed at said terminal of said latch and applying the level shifted latch voltage to said first transistor, when said latch is at said second state, wherein said first level shifter comprises a zener diode operating in a breakdown mode of operation; and an output fourth transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a level of said first input voltage when said latch is at one of said first and second states.

Claim 7

A level translator, comprising: a source of a switching, first input voltage; a first transistor responsive to said first switching input voltage for performing a switching operation; a pair of second and third transistors cross-coupled to each other to form a latch; a first level shifter for level shifting in a first direction a voltage developed in said first transistor and for applying the level shifted voltage to a terminal of said latch to establish said latch at a first state when said first input voltage is at a first state, such that when said first input voltage is at a second state, said input voltage causes said latch to be at a second state, said level shifter level shifting in an opposite direction a voltage that is developed at said terminal of said latch and applying the level shifted latch voltage to said first transistor, when said latch is at said second state, wherein said first level shifter comprises a zener diode operating in a breakdown mode of operation; and an output fourth transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a level of said first input voltage when said latch is at one of said first and second states.

Claim 8

A level translator according to claim 4 wherein a control terminal of a given one of said pair of said second and third transistors is coupled to a main current conducting terminal of said first transistor via a zener diode.

Claim 9

A level translator according to claim 1 wherein a main current conducting terminal of one of said pair of second and third transistors and said output transistor are coupled to a source of a second input voltage and a control terminal of said output transistor is coupled to a main current conducting terminal of one of said pair of second and third transistors.

Claim 10

A level translator according to claim 1 further comprising, a second output transistor operating in a complementary manner with respect to said first output transistor to produce said output voltage when said first output transistor is prevented from generating said output voltage.

Claim 11

A level translator according to claim 1 wherein a magnitude of said output voltage is determined by a second input voltage that is coupled to a main current conducting terminal of said output transistor and is unaffected by an amount by which said level shifted voltage is level shifted.

Claim 12

A level translator according to claim 1 wherein said level shifted voltage developed in said first transistor is coupled to a control terminal of one transistor of said pair of second and third transistors and is level shifted in a manner to reduce a voltage difference between said control terminal and a main current conducting terminal of said one transistor of said pair of transistors.

Claim 13

A level translator according to claim 1 wherein said level shifted latched voltage is coupled to a main current conducting terminal of said first transistor and is level shifted in a manner to reduce a voltage difference between a pair of main current conducting terminals of said first transistor.

Claim 14

A level translator according to claim 1 further comprising, a fifth transistor operating in a complementary manner with respect to said first transistor and a second level shifter for level shifting a voltage that is developed in said fifth transistor and for applying the level shifted voltage of said second level shifter to said latch for establishing said latch at said second state.

Claim 15

A level translator according to claim 1 wherein said first level shifter comprises a resistor network operating as a voltage divider for voltage dividing said voltage that is developed at said terminal of said latch to produce said level shifted voltage from a portion of said voltage that is developed at said terminal of said latch.

Claim 16

A level translator, comprising: a source of a first input voltage; a pair of first and second transistors coupled to each other and operating in a complementary manner to form a latch such that a first main current conducting terminal of a given one of said first pair of transistors is coupled to said source of said first input voltage and a second main current conducting terminal of said given one is coupled to a control terminal of the other one; a source of a switching, second input voltage; a pair of third and fourth transistors responsive to said second input voltage and operating in a complementary manner; a first zener diode coupled between a control terminal of said second transistor and a main current conducting terminal of said third transistor to provide level shifting; a second zener diode coupled between a control terminal of said first transistor and a main current conducting terminal of said fourth transistor to provide level shifting; and an output transistor having a control terminal that is coupled to a main current conducting terminal of one of said pair of said first and second transistors and a main current conducting terminal that is coupled to said source of said first input voltage for generating an output voltage that is determined by said first input voltage and that is level shifted with respect to a corresponding level of said second input voltage.

Claim 17

A level translator, comprising: a source of a first input voltage; a pair of first and second transistors coupled to each other and operating in a complementary manner to form a latch such that a first main current conducting terminal of a given one of said first pair of transistors is coupled to said source of said first input voltage and a second main current conducting terminal of said given one is coupled to a control terminal of the other one; a source of a switching, second input voltage; a pair of third and fourth transistors responsive to said second input voltage and operating in a complementary manner; a first zener diode coupled between a control terminal of said second transistor and a main current conducting terminal of said third transistor to provide level shifting; a second zener diode coupled between a control terminal of said first transistor and a main current conducting terminal of said fourth transistor to provide level shifting; and an output transistor having a control terminal that is coupled to a main current conducting terminal of one of said pair of said first and second transistors and a main current conducting terminal that is coupled to said source of said first input voltage for generating an output voltage that is determined by said first input voltage and that is level shifted with respect to a corresponding level of said second input voltage.

Claim 18

A level translator, comprising: a source of a first input voltage having, selectively, first and second levels; a first output transistor coupled to said source for selectively generating an output voltage at levels that are related to said first and second levels, respectively, when said first output transistor is enabled; a latch coupled to a control terminal of said first output transistor for enabling said first output transistor when said latch is at a first state and for disabling said output transistor when said latch is at a second state; a source of a switching signal; a level shifter responsive to said switching signal and coupled to said latch for level shifting said switching signal when said switching signal is at a first level and for applying the level shifted signal to said latch to establish said latch at one of said first and second states such that when said switching signal is at a second level said switching signal is applied to said latch to establish said latch at the other one of said first and second states; and a switch coupled to said level shifter for selectively varying said level shifted signal in accordance with said first and second levels such that when said first input voltage is at said first level said level shifter level shifts said switching signal by a first amount and when said first input voltage is at said second level, said level shifter level shifts said switching signal by a different amount.

Claim 19

A level translator, comprising: a source of a first input voltage having, selectively, first and second levels; a first output transistor coupled to said source for selectively generating an output voltage at levels that are related to said first and second levels, respectively, when said first output transistor is enabled; a latch coupled to a control terminal of said first output transistor for enabling said first output transistor when said latch is at a first state and for disabling said output transistor when said latch is at a second state; a source of a switching signal; a level shifter responsive to said switching signal and coupled to said latch for level shifting said switching signal when said switching signal is at a first level and for applying the level shifted signal to said latch to establish said latch at one of said first and second states such that when said switching signal is at a second level said switching signal is applied to said latch to establish said latch at the other one of said first and second states; and a switch coupled to said level shifter for selectively varying said level shifted signal in accordance with said first and second levels such that when said first input voltage is at said first level said level shifter level shifts said switching signal by a first amount and when said first input voltage is at said second level, said level shifter level shifts said switching signal by a different amount.

Claim 20

A level translator according to claim 14 wherein said level shifter comprises first and second zener diodes and wherein said switch selects one of said zener diodes in accordance with the level of said first input voltage.

Claim 21

A level translator according to claim 14 further comprising a second output transistor for generating said output voltage at a third level when said first output transistor is disabled.

Claim 22

A level translator for controlling a transmission gate, comprising: a first pair of transistors coupled to each other to form said transmission gate and to a source of a first input voltage for applying said first input voltage to a utilization circuit when said transmission gate is enabled and for decoupling said source of said first input voltage from said utilization circuit when said transmission gate is disabled; a second pair of transistors coupled to each other to form a latch; a source of a switching input signal; and a level shifter responsive to said switching input signal and coupled to said latch for level shifting said input signal and for applying the level shifted input signal to said latch to vary states of said latch in accordance with levels of said input signal, said latch being coupled to said transmission gate such that, when said latch is at a first state, a first control voltage and a second control voltage of said transmission gate are at first and second levels, respectively, to enable said transmission gate and, when said latch is at a second state, said first and second control voltages are at third and fourth levels, respectively, to disable said transmission gate, at least one of said third and fourth levels being significantly different from each one of said first and second levels.

Claim 23

A level translator for controlling a transmission gate, comprising: a first pair of transistors coupled to each other to form said transmission gate and to a source of a first input voltage for applying said first input voltage to a utilization circuit when said transmission gate is enabled and for decoupling said source of said first input voltage from said utilization circuit when said transmission gate is disabled; a second pair of transistors coupled to each other to form a latch; a source of a switching input signal; and a level shifter responsive to said switching input signal and coupled to said latch for level shifting said input signal and for applying the level shifted input signal to said latch to vary states of said latch in accordance with levels of said input signal, said latch being coupled to said transmission gate such that, when said latch is at a first state, a first control voltage and a second control voltage of said transmission gate are at first and second levels, respectively, to enable said transmission gate and, when said latch is at a second state, said first and second control voltages are at third and fourth levels, respectively, to disable said transmission gate, at least one of said third and fourth levels being significantly different from each one of said first and second levels.

Claim 24

A level translator according to claim 17 wherein said level shifter further comprises a third pair of transistors responsive to said switching input signal and first and second resistors coupled in series between a main current conducting terminal of one of said third pair of transistors and a main current conducting terminal of one of said second pair of transistors and third and fourth resistors coupled in series between a main current conducting terminal of the other one of said third pair of transistors and a main current conducting terminal of the other one of said second pair of transistors and wherein a fifth resistor is coupled between a junction terminal of said first and second resistors and a junction terminal of said third and fourth resistors.

Claim 25

A level translator according to claim 17 wherein each of said first, second, third and fourth levels is significantly different from each of the other ones.

Claim 26

A level translator, comprising: a source of a switching input signal; a source of first, second and third voltages; a first level translating stage; a second level translating stage responsive to said input signal and coupled to said source for selectively applying said first and second voltages to an input of said first level translating stage when said input signal is at first and second states, respectively, said first level translating stage generating an output signal at a first level when said first voltage is applied to said input, at a second level, when said second voltage is applied to said input and at a third level when said input signal is at a third state such that each of said first, second and third levels is level translated with respect to a level of said input signal.

Claim 27

A level translator, comprising: a source of a switching input signal; a source of first, second and third voltages; a first level translating stage; a second level translating stage responsive to said input signal and coupled to said source for selectively applying said first and second voltages to an input of said first level translating stage when said input signal is at first and second states, respectively, said first level translating stage generating an output signal at a first level when said first voltage is applied to said input, at a second level, when said second voltage is applied to said input and at a third level when said input signal is at a third state such that each of said first, second and third levels is level translated with respect to a level of said input signal.

Claim 28

A level translator, comprising: a source of a switching input voltage; a pair of transistors responsive to said switching input voltage for performing a switching operation in a complementary manner; a latch; a zener diode bridge for applying second and third voltages developed in said pair of transistors, respectively, to said latch to establish said latch at a first state when said input voltage is at a first state, such that when said input voltage is at a second state, said input voltage causes said latch to be at a second state; and an output third transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a lever of said input voltage when said latch is at one of said first and second states.

Claim 29

A level translator, comprising: a source of a switching input voltage; a pair of transistors responsive to said switching input voltage for performing a switching operation in a complementary manner; a latch; a zener diode bridge for applying second and third voltages developed in said pair of transistors, respectively, to said latch to establish said latch at a first state when said input voltage is at a first state, such that when said input voltage is at a second state, said input voltage causes said latch to be at a second state; and an output third transistor responsive to a voltage developed in said latch for generating an output voltage that is level translated with respect to a lever of said input voltage when said latch is at one of said first and second states.