US5510296A
Expired / Lapsed
US
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Manufacturable process for tungsten polycide contacts using amorphous silicon
Assignee: Vanguard International Semiconductor Corp
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Filing: 1995-04-27
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Granted: 1996-04-23
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Expires: 2015-04-27
Abstract
Abstract A method for creating manufacturable polycide contacts, for use in advanced semiconductor designs using images as small as 0.35 μM, has been developed. An amorphous silicon film, is used as an underlay, to assist in the growth of an overlying tungsten silicide layer. The tungsten silicide deposition is performed using tungsten hexafluoride and silane, and in conjunction with the amorphous silicon underlay, results excellent step coverage in the narrow contact hole. A nitrogen anneal, using high flow rates, optimizes the adhesion characteristics of the tungsten polycide structure.
Inventors
- 👤 Haw Yen
- 👤 Shaw-Tseng Hsia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/042; H10W20/045; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/0113; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/414; H10W20/033; H10W20/047; H10W20/051; H10W20/052; H10W20/0526; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
187 words
A method for fabricating a MOSFET device on a semiconductor substrate, using a polycide coated hole to provide electrical contact between active device regions in the substrate, and the interconnect metallizations, comprising the steps of: providing the active device elements in said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes said active device elements; photolithe, graphic processing to open a region in photoresist, exposing said first dielectric layer, directly overlying said active device element; anisotropic removal of said first dielectric layer, in said opened region of photoresist, to create a contact hole to said active device element; surface cleaning of said active device element, in said contact hole opening; depositing a layer of amorphous silicon on said active device element, in said contact hole opening, and on the surface of said first dielectric layer; ion implanting a first conductivity imparting dopant into said silicon layer; surface cleaning of said silicon layer; depositing a metal silicide layer on said silicon layer, to form a metal polycide; patterning of said metal polycide to form contact structure; and annealing of said metal polycide contact structure.
Claim 2
Independent Claim
187 words
A method for fabricating a MOSFET device on a semiconductor substrate, using a polycide coated hole to provide electrical contact between active device regions in the substrate, and the interconnect metallizations, comprising the steps of: providing the active device elements in said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes said active device elements; photolithe, graphic processing to open a region in photoresist, exposing said first dielectric layer, directly overlying said active device element; anisotropic removal of said first dielectric layer, in said opened region of photoresist, to create a contact hole to said active device element; surface cleaning of said active device element, in said contact hole opening; depositing a layer of amorphous silicon on said active device element, in said contact hole opening, and on the surface of said first dielectric layer; ion implanting a first conductivity imparting dopant into said silicon layer; surface cleaning of said silicon layer; depositing a metal silicide layer on said silicon layer, to form a metal polycide; patterning of said metal polycide to form contact structure; and annealing of said metal polycide contact structure.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said active device element in said semiconductor substrate, is an N type doped region.
Claim 4
Dependent Claim
35 words
The method of claim 1, wherein said first dielectric layer is silicon oxide, deposited using LPCVD, at a temperature between about 400° to 600° C., to a thickness between about 3000 and 4000 to Angstroms.
Claim 5
Dependent Claim
54 words
The method of claim 1, wherein the surface of said active device element, in said contact hole opening, is cleaned using a solution of 200 parts by weight water, to 1 part by weight hydrofluoric acid, at a temperature between about 20° and 25° C., for a time between about 60 and 120 seconds.
Claim 6
Dependent Claim
34 words
The method of claim 1, wherein said silicon layer is amorphous silicon, obtained using LPCVD processing at a temperature between about 500° and 550° C., to a thickness between about 300 and 700 Angstroms.
Claim 7
Dependent Claim
32 words
The method of claim 1, wherein said first conductivity imparting dopant is phosphorous, implanted at an energy between about 30 and 40 Kev, at a dose between about 1E15 and 5E15 atoms/cm2.
Claim 8
Dependent Claim
46 words
The method of claim 1, wherein the surface of said amorphous silicon is cleaned using a solution of 200 parts by weight water, to 1 part hydrofluoric acid, at a temperature between about 20° and 25° C., for a time between about 60 and 120 seconds.
Claim 9
Dependent Claim
39 words
The method of claim 1, wherein said metal silicide is tungsten silicide, obtained via LPCVD processing, using silane and tungsten hexafluoride, at a temperature between about 300° and 400° C., to a thickness between about 1000 and 2000 Angstroms.
Claim 10
Dependent Claim
15 words
The method of claim 1, wherein said metal polycide structure is formed using RIE patterning.
Claim 11
Dependent Claim
17 words
The method of claim 1, wherein said metal polycide contact structure is formed using chemical mechanical polishing.
Claim 12
Dependent Claim
46 words
The method of claim 1, wherein said metal polycide structure is annealed in nitrogen, at a temperature between about 750° and 850° C., for a time between about 30 and 60 minutes at a nitrogen flow between about 25 to 30 standard liters per minute, (slm).
Claim 13
Independent Claim
195 words
A method for fabricating a MOSFET device or, a semiconductor substrate, using a tungsten polycide coated contact hole to provide electrical contact between source and drain regions in the substrate, and interconnect metallizations, comprising the steps of: providing source and drain regions in said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes exposed said source and drain regions; photolithographic processing to open a region in photoresist, exposing said first dielectric layer, directly overlying said source and drain region; anisotropic removal of said first dielectric layer, in said opened region of photoresist, to create a contact hole to said source and drain region; surface cleaning of said source and drain region, in said contact hole opening; depositing a layer of amorphous silicon on said source and drain region, in said contact hole opening, and on surface of said first dielectric layer; ion implanting a first conductivity imparting dopant into said amorphous silicon layer; surface cleaning of said amorphous silicon layer; depositing a tungsten silicide layer on said amorphous silicon layer, to form tungsten polycide; patterning of said tungsten polycide to form contact structure; and annealing of said tungsten polycide contact structure.
Claim 14
Independent Claim
195 words
A method for fabricating a MOSFET device or, a semiconductor substrate, using a tungsten polycide coated contact hole to provide electrical contact between source and drain regions in the substrate, and interconnect metallizations, comprising the steps of: providing source and drain regions in said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes exposed said source and drain regions; photolithographic processing to open a region in photoresist, exposing said first dielectric layer, directly overlying said source and drain region; anisotropic removal of said first dielectric layer, in said opened region of photoresist, to create a contact hole to said source and drain region; surface cleaning of said source and drain region, in said contact hole opening; depositing a layer of amorphous silicon on said source and drain region, in said contact hole opening, and on surface of said first dielectric layer; ion implanting a first conductivity imparting dopant into said amorphous silicon layer; surface cleaning of said amorphous silicon layer; depositing a tungsten silicide layer on said amorphous silicon layer, to form tungsten polycide; patterning of said tungsten polycide to form contact structure; and annealing of said tungsten polycide contact structure.
Claim 15
Dependent Claim
21 words
The method of claim 12, wherein said source and drain region in said semiconductor substrate, is an N type doped region.
Claim 16
Dependent Claim
35 words
The method of claim 12, wherein said first dielectric layer is silicon oxide, deposited using LPCVD processing, at a temperature between about 400° and 600° C., to a thickness between about 3000 and 4000 Angstroms.
Claim 17
Dependent Claim
53 words
The method of claim 12, wherein surface of said source and drain region, in said contact hole, is cleaned using a solution of 200 parts by weight water to 1 part by weight hydrofluoric acid, at a temperature between about 20° and 25° C., for a time between about 60 and 120 sec.
Claim 18
Dependent Claim
32 words
The method of claim 12, wherein said amorphous silicon layer is deposited using LPCVD, at a temperature between about 500° and 550° C., to a thickness between about 300 and 700 Angstroms.
Claim 19
Dependent Claim
32 words
The method of claim 12, wherein said first conductivity imparting dopant is phosphorous, implanted at an energy between about 30 and 40 Kev, at a dose between about 1E15 and 5E15 atoms/cm2.
Claim 20
Dependent Claim
48 words
The method of claim 12, wherein surface of said amorphous silicon layer is cleaned using a solution of 200 parts by weight water, to 1 part by weight hydrofluoric acid, at a temperature between about 20° and 25° C., for a time between about 60 and 120 seconds.
Claim 21
Dependent Claim
39 words
The method of claim 12., wherein said tungsten silicide layer is formed by LPCVD processing, using silane and tungsten hexafluoride, at a temperature between about 300° and 400 ° C., to a thickness between about 1000 and 2000 Angstroms.
Claim 22
Dependent Claim
15 words
The method of claim 12, wherein said tungsten polycide structure is formed by RIE patterning.
Claim 23
Dependent Claim
17 words
The method of claim 18, wherein said tungsten polycide contact structure is formed using chemical mechanical polishing.
Claim 24
Dependent Claim
42 words
The method of claim 12, wherein said tungsten polycide structure is annealed in nitrogen, at a temperature between about 750° and 850° C., for a time between about 30 and 60 minutes, at a nitrogen flow between about 25 and 30 slm.
References Cited (Backward Citations)
US4968645A
Cited
US4800176A
Cited
US5371041A
Cited
US5374591A
Cited
US5340761A
Cited
US5366929A
Cited
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