Semiconductor memory device

Claim 2

A semiconductor memory device, comprising: a memory cell array (MCA) having a plurality of memory cells arranged into a matrix pattern and having a plurality of pairs of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs; a row decode circuit (RD) for decoding a row address inputted thereto to select the memory cells arranged in a row direction; (L×k)-units of data lines (DLN), wherein a number (L×k) of said data lines is smaller than the number of the bit line pairs, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines; a plurality of column gates, each connected between a respective one of said data lines and each of the bit line pairs and turned on or off to connect or disconnect the respective one of said data lines to and from each of the bit line pairs; a plurality of column select lines (CSL), each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-unit column gates simultaneously; a column gate select circuit (CGS) for activating said column select lines; a data buffer connected to said data lines for buffering and outputting data on said data lines; a first register group having a plurality of registers, each for storing one-bit data outputted by said data buffer; a transfer circuit connected between said data buffer and said first register group, for scrambling said data outputted by said data buffer and storing the scrambled data in the registers of said first register group in a predetermined sequence; a scanning circuit for scanning the registers in the predetermined sequence to output data stored in the registers; and an output buffer circuit for buffering and outputting data provided by said scanning circuit.

Claim 3

The semiconductor memory device of claim 1, which further comprises a second register group having a plurality of registers and operable in a same manner as said first register group, said first and second register groups being used alternately.

Claim 4

The semiconductor memory device of claim 2, wherein said transfer circuit includes a first transfer circuit unit connected between said data buffer and said first register group and a second transfer circuit unit connected between said data buffer and said second register group.

Claim 5

The semiconductor memory device of claim 2, wherein k=2 and L=2.

Claim 6

The semiconductor memory device of claim 2, wherein k=3 and L=2.

Claim 7

The semiconductor memory device of claim 1, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 8

The semiconductor memory device of claim 6, wherein k=2 and L=2.

Claim 9

The semiconductor memory device of claim 6, wherein k=3 and L=2.

Claim 10

The semiconductor memory device of claim 1, wherein said column gate select circuit selects L-units of said column select lines simultaneously.

Claim 11

The semiconductor memory device of claim 9, which further comprises a second register group having a plurality of registers and operable in a same manner as said first register group, said first and second register groups being used alternately.

Claim 12

The semiconductor memory device of claim 10, wherein said transfer circuit includes a first transfer circuit unit connected between said data buffer and said first register group and a second transfer circuit unit connected between said data buffer and said second register group.

Claim 13

The semiconductor memory device of claim 11, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 14

The semiconductor memory device of claim 10, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 15

The semiconductor memory device of claim 9, wherein said column gate select circuit simultaneously selects a k-th column select line and at least a (k+1)-th column select line.

Claim 16

The semiconductor memory device of claim 14, which further comprises a second register group having a plurality of registers and operable in a same manner as said first register group, said first and second register groups being used alternately.

Claim 17

The semiconductor memory device of claim 15, wherein said transfer circuit includes a first transfer circuit unit connected between said data buffer and said first register group and a second transfer circuit unit connected between said data buffer and said second register group.

Claim 18

The semiconductor memory device of claim 15, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 19

The semiconductor memory device of claim 14, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 20

The semiconductor memory device of claim 9, wherein k=2 and L=2.

Claim 21

The semiconductor memory device of claim 9, wherein k=3 and L=2.

Claim 22

The semiconductor memory device of claim 9, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 23

The semiconductor memory device of claim 1, wherein k=2 and L=2.

Claim 24

The semiconductor memory device of claim 1, wherein k=3 and L=2.

Claim 25

A semiconductor memory device, comprising: a memory cell array (MCA) having a plurality of memory cells arranged into a matrix pattern and having a plurality of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs; a row decode circuit (RD) for decoding a row address inputted thereto to select the memory cells arranged in a row direction; (2k)-units of data lines (DLN), wherein (2k) of said data lines is smaller than n, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines; n-units of column gates, each connected between each of said data lines and each of the bit line pairs and turn on or off to connect or disconnect each of said data lines to and from of the bit line pairs; n/k-units of column select lines each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-units of said column gates simultaneously, the first to fourth column select lines (C1, C2, C3, C4) turning on said first and second column gates, said third and fourth column gates, said fifth and sixth column gates, and said seventh and eighth column gates, respectively to select the corresponding first and second, third and fourth, fifth and sixth, and seventh and eighth bit line pairs, respectively; a column gate select circuit (CGS) for activating said column select lines; a data buffer connected to said data lines for buffering and outputting data on said data lines; register means having 2k units of registers, each for storing one-bit data outputted by said buffer; a transfer circuit connected between said data buffer and said register means, for scrambling said 2k-units of data outputted by said data buffer and storing the scrambled data in the registers of said register means in a predetermined sequence; a scanning circuit for scanning the registers in the predetermined sequence to output data stored in the registers; and an output buffer circuit for buffering and outputting data provided by said scanning circuit, wherein in a cyclic and continuous selection of the bit line pairs, i) when the bit line pair to be selected first is selected by said first column select line C1, said column gate select circuit selects said column select lines in sequence of (C1, C2), (C2, C3), (C3, C4), (C4, C1); ii) when the bit line pair to be selected first is selected by said second column select line C2, said column gate select circuit selects said column select lines in sequence of (C2, C3), (C3, C4), (C4, C1), (C1, C2); iii) when the bit line pair to be selected first is selected by said third column select line C3, said column gate select circuit selects said column select lines in sequence of (C3, C4), (C4, C1) (C1, C2), (C2, C3); and iv) when the bit line pair to be selected first is selected by said fourth column select line C4, said column gate select circuit selects said column select lines in sequence of (C4, C1), (C1, C2), (C2, C3), (C3, C4).

Claim 26

A semiconductor memory device, comprising: a memory cell array (MCA) having a plurality of memory cells arranged into a matrix pattern and having a plurality of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs; a row decode circuit (RD) for decoding a row address inputted thereto to select the memory cells arranged in a row direction; (2k)-units of data lines (DLN), wherein (2k) of said data lines is smaller than n, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines; n-units of column gates, each connected between each of said data lines and each of the bit line pairs and turn on or off to connect or disconnect each of said data lines to and from of the bit line pairs; n/k-units of column select lines each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-units of said column gates simultaneously, the first to fourth column select lines (C1, C2, C3, C4) turning on said first and second column gates, said third and fourth column gates, said fifth and sixth column gates, and said seventh and eighth column gates, respectively to select the corresponding first and second, third and fourth, fifth and sixth, and seventh and eighth bit line pairs, respectively; a column gate select circuit (CGS) for activating said column select lines; a data buffer connected to said data lines for buffering and outputting data on said data lines; register means having 2k units of registers, each for storing one-bit data outputted by said buffer; a transfer circuit connected between said data buffer and said register means, for scrambling said 2k-units of data outputted by said data buffer and storing the scrambled data in the registers of said register means in a predetermined sequence; a scanning circuit for scanning the registers in the predetermined sequence to output data stored in the registers; and an output buffer circuit for buffering and outputting data provided by said scanning circuit, wherein in a cyclic and continuous selection of the bit line pairs, i) when the bit line pair to be selected first is selected by said first column select line C1, said column gate select circuit selects said column select lines in sequence of (C1, C2), (C2, C3), (C3, C4), (C4, C1); ii) when the bit line pair to be selected first is selected by said second column select line C2, said column gate select circuit selects said column select lines in sequence of (C2, C3), (C3, C4), (C4, C1), (C1, C2); iii) when the bit line pair to be selected first is selected by said third column select line C3, said column gate select circuit selects said column select lines in sequence of (C3, C4), (C4, C1) (C1, C2), (C2, C3); and iv) when the bit line pair to be selected first is selected by said fourth column select line C4, said column gate select circuit selects said column select lines in sequence of (C4, C1), (C1, C2), (C2, C3), (C3, C4).

Claim 27

The semiconductor memory device of claims 24, wherein said register means has two register groups, each including two registers, the respective register groups being interleaved.

Claim 28

The semiconductor memory device of claim 25, wherein said transfer circuit includes two transfer circuit units each connected between said data buffer and each of the register groups.

Claim 29

The semiconductor memory device of claim 24, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 30

The semiconductor memory device of claim 24, wherein k=2.

Claim 31

The semiconductor memory device of claim 24, wherein k=3.

Claim 32

A semiconductor memory device, comprising: a memory cell array (MCA) having a plurality of memory cells arranged into a matrix pattern and having a plurality of pairs of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs; (L×k)-units of data lines (DLN), wherein a number (L×k) of said data lines is smaller than the number of the bit line pairs, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines; a plurality of column gates, each connected between a respective one of said data lines and each of the bit line pairs and turned on or off to connect or disconnect the respective one of said data lines to and from each of the bit line pairs; a plurality of column select lines (CSL), each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-unit column gates simultaneously; a column gate select circuit (CGS) for activating said column select lines; a first register group having a plurality of registers, each being connected to each of said data lines, each of said registers storing one-bit data on each of said data lines; a transfer circuit connected between said data lines and said first register group, for scrambling said (L×k)-units of data on said data lines and storing the scrambled data in the registers of said first register group in a predetermined sequence; and a scanning circuit for scanning the registers in the predetermined sequence to output data stored in the registers.

Claim 33

A semiconductor memory device, comprising: a memory cell array (MCA) having a plurality of memory cells arranged into a matrix pattern and having a plurality of pairs of bit lines, a plurality of the memory cells arranged in a column direction being connected to each of the bit line pairs; (L×k)-units of data lines (DLN), wherein a number (L×k) of said data lines is smaller than the number of the bit line pairs, each of the bit line pairs being connected to any of said data lines and thereby a plurality of the bit line pairs being connected in common to each of said data lines; a plurality of column gates, each connected between a respective one of said data lines and each of the bit line pairs and turned on or off to connect or disconnect the respective one of said data lines to and from each of the bit line pairs; a plurality of column select lines (CSL), each connected to control terminals of mutually-adjacent k-units of said column gates, for turning on or off said k-unit column gates simultaneously; a column gate select circuit (CGS) for activating said column select lines; a first register group having a plurality of registers, each being connected to each of said data lines, each of said registers storing one-bit data on each of said data lines; a transfer circuit connected between said data lines and said first register group, for scrambling said (L×k)-units of data on said data lines and storing the scrambled data in the registers of said first register group in a predetermined sequence; and a scanning circuit for scanning the registers in the predetermined sequence to output data stored in the registers.

Claim 34

The semiconductor memory device of claim 30, which further comprises a second register group having a plurality of registers and operable in a same manner as said first register group, and comprises a second transfer circuit connected between said data lines and said second register group, for scrambling (L×k)-units of data on said data lines and storing the scrambled data in the registers of said second register group in a predetermined sequence, said first and second register groups being used alternately.

Claim 35

The semiconductor memory device of claim 31, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 36

The semiconductor memory device of claim 30, wherein said column gate select circuit selects L-units of said column select lines simultaneously.

Claim 37

The semiconductor memory device of claim 33, wherein said column gate select circuit simultaneously selects said k-th column select line and said at least (k+1)-th column select line.

Claim 38

The semiconductor memory device of claim 34, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 39

The semiconductor memory device of claim 33, wherein said scanning circuit is activated on the basis of a clock signal.

Claim 40

The semiconductor memory device of claim 30, wherein said scanning circuit is activated on the basis of a clock signal.