EP0154314A2
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EP
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Data I/O circuit with higher integration density for DRAM
Assignee: Oki Electric Industry Co Ltd
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Filing: 1985-03-01
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Granted: —
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Expires: 2005-03-01
Abstract
Abstract A data input/output circuit operates in an operation cycle in which, when a first latch circuit connected to a first data bus issues 1-bit information to a data output buffer, next 1-bit information is latched in a second latch circuit connected to a second data bus and simultaneously the first data bus is precharged, and in an operation cycle in which, when 1-bit data stored in the second latch circuit is issued to the data output buffer, next 1-bit data is latched in the first latch circuit and simultaneously the second data bus is precharged. Therefore, when one of the latch circuits issues data to the data output buffer, the other latch circuit latches data and is in a standby condition. An access time in which to issue data from bit lines to the data buses is greatly reduced notwithstanding that only two data buses are employed. Accordingly, the chip area occupied by the data buses can be reduced appreciably.
Inventors
- 👤 Atsushi Oki Electric Industry Co. Ltd. Takasugi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
357 words
A data input/output circuit for serially accessing N-bit data (N > 4) for a DRAM circuit, comprising: (a) a first data bus composed of a pair of conductors for transferring data; (b) a second data bus composed of a pair of conductors for transferring data; (c) a first precharge circuit for charging said first data bus in response to a first timing control signal; (d) a second precharge circuit for charging said second data bus in response to a second timing control signal; (e) a first group of N/2 switches independently controllable by a group of third timing control signals, respectively, said switches of the first group being coupled between respective bit lines and said first data bus for transferring 1-bit information on said bit lines to said first data bus in response to the respective third timing control signals; (f) a second group of N/2 switches independently controllable by a group of fourth timing control signals, respectively, said switches of the second group being coupled between the respective bit lines and said second data bus for transferring 1-bit information on said bit lines to said first data bus in response to the fourth timing control signals; (g) a first latch circuit for latching and amplifying the information on said first data bus under the control of a fifth timing control signal; (h) a second latch circuit for latching and amplifying the information on said second data bus under the control of a sixth timing control signal; (i) third switch means for selectively issuing output information of said first latch circuit under the control of a seventh timing control signal; (j1 fourth switch means for selectively issuing output information of said first latch circuit under the control of an eighth timing control signal; (k) a data output buffer for converting the output information from said third or fourth switch means into 1-bit information and issuing the same under the control of one logic level of an enable signal; and (1) a timing signal generator circuit for generating said first, second, fifth, sixth, seventh, eighth timing control signals and said groups of third and fourth timing control signals.
Claim 2
Dependent Claim
357 words
A data input/output circuit for serially accessing N-bit data (N > 4) for a DRAM circuit, comprising: (a) a first data bus composed of a pair of conductors for transferring data; (b) a second data bus composed of a pair of conductors for transferring data; (c) a first precharge circuit for charging said first data bus in response to a first timing control signal; (d) a second precharge circuit for charging said second data bus in response to a second timing control signal; (e) a first group of N/2 switches independently controllable by a group of third timing control signals, respectively, said switches of the first group being coupled between respective bit lines and said first data bus for transferring 1-bit information on said bit lines to said first data bus in response to the respective third timing control signals; (f) a second group of N/2 switches independently controllable by a group of fourth timing control signals, respectively, said switches of the second group being coupled between the respective bit lines and said second data bus for transferring 1-bit information on said bit lines to said first data bus in response to the fourth timing control signals; (g) a first latch circuit for latching and amplifying the information on said first data bus under the control of a fifth timing control signal; (h) a second latch circuit for latching and amplifying the information on said second data bus under the control of a sixth timing control signal; (i) third switch means for selectively issuing output information of said first latch circuit under the control of a seventh timing control signal; (j1 fourth switch means for selectively issuing output information of said first latch circuit under the control of an eighth timing control signal; (k) a data output buffer for converting the output information from said third or fourth switch means into 1-bit information and issuing the same under the control of one logic level of an enable signal; and (1) a timing signal generator circuit for generating said first, second, fifth, sixth, seventh, eighth timing control signals and said groups of third and fourth timing control signals.
Claim 3
Dependent Claim
36 words
A data input/output circuit according to claim 1, wherein each of said first and second precharge circuits, said N/2 switches of said first and second groups, and said third and fourth switch means comprises MOS transistors.
Claim 4
Dependent Claim
30 words
A data input/output circuit according to claim 2, wherein said first group of N/2 switches comprises two first switches, and said second group of N/2 switches comprises two second switches.
Claim 5
Dependent Claim
82 words
a 4. A data input/output circuit according to claim 2, having a readout cycle in which, when said first latch circuit latches second data of said first data bus, first data of said second latch circuit is issued through said data output buffer and said second data bus is precharged, and when said second latch circuit latches third data, said second data latched by said second latch circuit is issued through said output data buffer and said first data bus is precharged.
Claim 6
Dependent Claim
83 words
A data input/output circuit according to claim 1, further including fifth switch means coupled to said first data bus and controllable by said seventh timing control signal, sixth switch means coupled to said second data bus and controllable by said eighth timing control signal, and a data input buffer for converting 1-bit input information into complementary signals and transferring the same to said fifth and sixth switch means under the control of another logic level of said enable signal. Explanation of some abbreviations:
References Cited (Backward Citations)
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