US5506383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer scale multi-chip module
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-02-10
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Granted: 1996-04-09
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Expires: 2015-02-10
Abstract
Abstract A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.
Inventors
- 👤 Yaw-Hwang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:56
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/614; H10D; H10D62/00; H10D62/10; H10D62/117; H10W70/099; H10W74/00; H10W74/10; H10W74/131; H10W74/142; H10W90/00; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/4913
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
414 words
A method of manufacturing a wafer scale multi-chip module comprising the following steps: (a) forming a semiconductor wafer substrate, said semiconductor substrate having a top surface and a bottom surface; (b) forming an electrically conductive interconnect network on said top surface of said semiconductor wafer substrate, said interconnect network having a plurality of openings with substantially vertical walls where semiconductor chips are to be placed; (c) forming contact pads on a top surface of said interconnect network; (d) forming a plurality of openings in said semiconductor wafer substrate corresponding to said openings in said interconnect network, said plurality of openings in said semiconductor wafer substrate being slightly larger than said openings in said interconnect network; (e) forming a plurality of integrated circuit chips, each of said plurality of integrated circuit chips having a top surface and a bottom surface; (f) forming contact pads on said top surface of each of said integrated circuit chips corresponding to inputs and outputs of said integrated circuit chips; (g) forming a groove along the perimeter of said top surface of each of said integrated circuit chips, said groove of each of said plurality of integrated circuit chips being slightly smaller than its corresponding opening in said interconnect network, the perimeter of each of said plurality of integrated circuit chips being slightly larger than its corresponding opening in said interconnect network; (h) flowing solder into said groove along the perimeter of said top surface of each of said plurality of integrated circuit chips; (i) mating each of said plurality of integrated circuit chips with its corresponding opening in said semiconductor wafer such that said top surface of each of said integrated circuit chips is substantially planar with said top surface of said interconnect network and said bottom surface of each of said integrated circuit chips is substantially planar with said bottom surface of said semiconductor wafer; (j) reflowing said solder between said groove of each of said integrated circuit chips and said interconnect network; (k) forming a passivation layer on said top surface of said interconnect network and said top surface of said interconnect network and said top surface of each of said integrated circuit chips; (l) forming contact pad vias in said passivation layer corresponding to said contact pads of said interconnect network and said contact pads of each of said integrated circuit chips; and (m) forming a conductive bridge between contact pads on said interconnect network and corresponding contact pads on each of said integrated circuit chips.
Claim 2
Independent Claim
414 words
A method of manufacturing a wafer scale multi-chip module comprising the following steps: (a) forming a semiconductor wafer substrate, said semiconductor substrate having a top surface and a bottom surface; (b) forming an electrically conductive interconnect network on said top surface of said semiconductor wafer substrate, said interconnect network having a plurality of openings with substantially vertical walls where semiconductor chips are to be placed; (c) forming contact pads on a top surface of said interconnect network; (d) forming a plurality of openings in said semiconductor wafer substrate corresponding to said openings in said interconnect network, said plurality of openings in said semiconductor wafer substrate being slightly larger than said openings in said interconnect network; (e) forming a plurality of integrated circuit chips, each of said plurality of integrated circuit chips having a top surface and a bottom surface; (f) forming contact pads on said top surface of each of said integrated circuit chips corresponding to inputs and outputs of said integrated circuit chips; (g) forming a groove along the perimeter of said top surface of each of said integrated circuit chips, said groove of each of said plurality of integrated circuit chips being slightly smaller than its corresponding opening in said interconnect network, the perimeter of each of said plurality of integrated circuit chips being slightly larger than its corresponding opening in said interconnect network; (h) flowing solder into said groove along the perimeter of said top surface of each of said plurality of integrated circuit chips; (i) mating each of said plurality of integrated circuit chips with its corresponding opening in said semiconductor wafer such that said top surface of each of said integrated circuit chips is substantially planar with said top surface of said interconnect network and said bottom surface of each of said integrated circuit chips is substantially planar with said bottom surface of said semiconductor wafer; (j) reflowing said solder between said groove of each of said integrated circuit chips and said interconnect network; (k) forming a passivation layer on said top surface of said interconnect network and said top surface of said interconnect network and said top surface of each of said integrated circuit chips; (l) forming contact pad vias in said passivation layer corresponding to said contact pads of said interconnect network and said contact pads of each of said integrated circuit chips; and (m) forming a conductive bridge between contact pads on said interconnect network and corresponding contact pads on each of said integrated circuit chips.
Claim 3
Dependent Claim
45 words
The method of manufacturing a wafer scale multi-chip module according to the steps of claim 1 comprising the further step of: (n) forming a heat sink on the bottom surface of said semiconductor wafer and the bottom surface of each of said integrated circuit chips.
Claim 4
Dependent Claim
32 words
The method of manufacturing a wafer scale multi-chip module according to the steps of claim 1 wherein said semiconductor wafer and said plurality of integrated circuit chips are comprised substantially of silicon.
Claim 5
Dependent Claim
73 words
The method of manufacturing a wafer scale multi-chip module according to the steps of claim 1 wherein said plurality of openings in said semiconductor wafer have walls with 45 degree angles between said top surface of said semiconductor wafer and said bottom surface of said semiconductor wafer such that resulting openings at said bottom surface of said semiconductor wafer are slightly wider than resulting openings at said top side of said semiconductor wafer.
Claim 6
Dependent Claim
49 words
The method of manufacturing a wafer scale multi-chip module according to the steps of claim 1 comprising the further step of: (n) filling any gap between said plurality of integrated circuit chips and said semiconductor wafer substrate with a silicon epoxy type substance in order to enhance module strength.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |