US5243498A
Expired / Lapsed
US
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Multi-chip semiconductor module and method for making and testing
Assignee: NXP USA Inc
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Filing: 1992-05-26
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Granted: 1993-09-07
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Expires: 2012-05-26
Abstract
Abstract A multi-chip semiconductor module (10,20) includes a plurality of semiconductor chips (13,13') mounted on a substrate (11) and a plurality of conductive vias (16) extending through the substrate (11). A conductive network (17) formed on the substrate and a plurality of leads (19) are mounted to edges of the substrate (11) and extend away from the substrate (11). Each of the leads (19) is electrically coupled to a contact pad (14) of an integrated circuit chip (13,13'), and each conductive vias (16) has a first end coupled to the conductive network (17) and a second end exposed on the bottom surface of the substrate (11) allowing electrical access to many of the contact pads (14) of the integrated circuit (13,13').
Inventors
- 👤 Robert J. Scofield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:33
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5445; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
168 words
A multi-chip semiconductor module comprising: a ceramic substrate having a top surface and a bottom surface; a plurality of semiconductor chips mounted on the top surface, wherein each chip has a plurality of contact pads formed thereon; a first set of conductive vias passing through the substrate near a periphery of the substrate; a plurality of leads attached to the periphery of the bottom surface of the substrate, wherein each lead is electrically coupled to one of the first set of conductive vias; a conductive network formed on the top surface of the substrate, wherein the conductive network includes a number of bonding pads and some of the contact pads of the are electrically coupled to the bonding pads of the conductive network; a second set of conductive vias located in a portion of the substrate, wherein each of the second set of vias is electrically coupled to the conductive network, wherein none of the second set of conductive vias is electrically coupled to one of the leads.
Claim 2
Dependent Claim
168 words
A multi-chip semiconductor module comprising: a ceramic substrate having a top surface and a bottom surface; a plurality of semiconductor chips mounted on the top surface, wherein each chip has a plurality of contact pads formed thereon; a first set of conductive vias passing through the substrate near a periphery of the substrate; a plurality of leads attached to the periphery of the bottom surface of the substrate, wherein each lead is electrically coupled to one of the first set of conductive vias; a conductive network formed on the top surface of the substrate, wherein the conductive network includes a number of bonding pads and some of the contact pads of the are electrically coupled to the bonding pads of the conductive network; a second set of conductive vias located in a portion of the substrate, wherein each of the second set of vias is electrically coupled to the conductive network, wherein none of the second set of conductive vias is electrically coupled to one of the leads.
Claim 3
Dependent Claim
42 words
The multi-chip semiconductor module of claim 1 further comprising a dielectric cover permanently attached to the bottom surface, wherein the second set of vias are covered by the dielectric cover and the plurality of leads are not covered by the dielectric cover.
Claim 4
Dependent Claim
20 words
The multi-chip semiconductor module of claim 1 further comprising wires bonded to the bonding pads and to the contact pads.
Claim 5
Dependent Claim
42 words
The multi-chip semiconductor module of claim 1 further comprising: a metallic bump formed on each contact pad, wherein each semiconductor chip is mounted face down on the substrate and each metallic bump is aligned to a predetermined location on the conductive network.
Claim 6
Dependent Claim
111 words
A multi-chip semiconductor module comprising: a substrate having a top surface and a bottom surface; a plurality of semiconductor chips mounted on the top surface, each chip having a plurality of contact pads formed thereon; a conductive network formed on the top surface of the substrate; a plurality of leads mounted to edges of the substrate and extending away from the substrate, wherein the each of the leads are electrically coupled to one of the contact pads; and a plurality of conductive vias extending through the substrate, wherein each via has a first end coupled to the conductive network and a second end exposed on the bottom surface of the substrate.
Claim 7
Dependent Claim
111 words
A multi-chip semiconductor module comprising: a substrate having a top surface and a bottom surface; a plurality of semiconductor chips mounted on the top surface, each chip having a plurality of contact pads formed thereon; a conductive network formed on the top surface of the substrate; a plurality of leads mounted to edges of the substrate and extending away from the substrate, wherein the each of the leads are electrically coupled to one of the contact pads; and a plurality of conductive vias extending through the substrate, wherein each via has a first end coupled to the conductive network and a second end exposed on the bottom surface of the substrate.
Claim 8
Dependent Claim
32 words
The multi-chip semiconductor module of claim 5 further comprising a dielectric cover mounted to the bottom surface of the substrate and covering the second end exposed of each of the conductive vias.
Claim 9
Dependent Claim
44 words
The multi-chip semiconductor module of claim 6 wherein each of the semiconductor chips further comprises a solder bump formed on each of the contact pads, and the chip is mounted face down with the solder bumps soldered to predetermined locations of the conductive network.
Claim 10
Independent Claim
207 words
A method of making and testing a multi-chip semiconductor module comprising the steps of: providing a substrate having a top surface and a bottom surface, wherein a plurality of conductive vias are formed through the substrate in predetermined locations; forming a conductive network on the substrate interconnecting selected vias, the conductive network including a number of bonding pads; mounting a plurality of semiconductor chips on the top surface, each chip having a plurality of contact pads formed thereon; electrically coupling each contact pad to one of the bonding pads of the conductive network; coupling a plurality of leads to the bottom surface of the substrate, wherein each lead is electrically coupled to one of the conductive vias and the number of leads is less than the number of conductive vias so that at least one conductive vias is not attached to one of the leads; testing the multi-chip module by temporarily coupling an external tester to the plurality of leads and to the at least one conductive vias that is not coupled to one of the leads; decoupling the multi-chip module from the external tester; and covering the at least one conductive vias that is not coupled to one of the leads with a dielectric cover plate.
Claim 11
Independent Claim
207 words
A method of making and testing a multi-chip semiconductor module comprising the steps of: providing a substrate having a top surface and a bottom surface, wherein a plurality of conductive vias are formed through the substrate in predetermined locations; forming a conductive network on the substrate interconnecting selected vias, the conductive network including a number of bonding pads; mounting a plurality of semiconductor chips on the top surface, each chip having a plurality of contact pads formed thereon; electrically coupling each contact pad to one of the bonding pads of the conductive network; coupling a plurality of leads to the bottom surface of the substrate, wherein each lead is electrically coupled to one of the conductive vias and the number of leads is less than the number of conductive vias so that at least one conductive vias is not attached to one of the leads; testing the multi-chip module by temporarily coupling an external tester to the plurality of leads and to the at least one conductive vias that is not coupled to one of the leads; decoupling the multi-chip module from the external tester; and covering the at least one conductive vias that is not coupled to one of the leads with a dielectric cover plate.
Claim 12
Dependent Claim
52 words
The method of claim 8 further comprising the steps of: providing a metallic bump on each contact pad of at least one of the semiconductor chips; and attaching the at least one of the semiconductor chip to the conductive network by soldering the metallic bumps to predetermined locations on the conductive network.
Claim 13
Dependent Claim
17 words
The method of claim 8 further comprising plating a bottom surface of the conductive vias with gold.
References Cited (Backward Citations)
US5088008A
Cited
US5151771A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |