US5506157A
Expired / Lapsed
US
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Method for fabricating pillar bipolar transistor
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1995-06-06
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Granted: 1996-04-09
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Expires: 2015-06-06
Abstract
Abstract Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.
Inventors
- 👤 Kyu-Hong Lee
- 👤 Jin-Hyo Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:58
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D62/00; H10D62/10; H10D62/17; H10D62/177; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
286 words
A method for fabricating a pillar bipolar transistor, the method comprising the steps of: etching a silicon substrate of a first conductivity type using a first patterned insulating layer as a mask to form a first and a second pillar structures separated by a trench region therein; injecting an impurity of a second conductivity type using a second patterned insulating layer as a mask to form a collector region under the first and second pillar structures and in the second pillar structure; sequentially depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base region; etching the first oxide layer formed on both sides of the first pillar structure to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; sequentially depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed on or over the first pillar structure to expose a surface of the first pillar structure; injecting an impurity of the first conductivity type in the first pillar structure to form a base region at a center portion thereof; injecting an impurity of the second conductivity type to form an emitter region at an upper portion of the first pillar structure; depositing a third polysilicon layer on the emitter region, the third polysilicon layer being formed wider than the emitter region; and forming self-aligned contact holes to form electrodes.
Claim 2
Independent Claim
286 words
A method for fabricating a pillar bipolar transistor, the method comprising the steps of: etching a silicon substrate of a first conductivity type using a first patterned insulating layer as a mask to form a first and a second pillar structures separated by a trench region therein; injecting an impurity of a second conductivity type using a second patterned insulating layer as a mask to form a collector region under the first and second pillar structures and in the second pillar structure; sequentially depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base region; etching the first oxide layer formed on both sides of the first pillar structure to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; sequentially depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed on or over the first pillar structure to expose a surface of the first pillar structure; injecting an impurity of the first conductivity type in the first pillar structure to form a base region at a center portion thereof; injecting an impurity of the second conductivity type to form an emitter region at an upper portion of the first pillar structure; depositing a third polysilicon layer on the emitter region, the third polysilicon layer being formed wider than the emitter region; and forming self-aligned contact holes to form electrodes.
Claim 3
Dependent Claim
32 words
The method according to claim 1, wherein the step of etching the silicon substrate is performed using a difference of etching rate between the first patterned insulating layer and the silicon substrate.
Claim 4
Dependent Claim
34 words
The method according to claim 1, wherein the step of injecting the impurity of the second conductivity type is performed using a diffusion difference between the second patterned insulating layer and the silicon substrate.
Claim 5
Dependent Claim
36 words
The method according to claim 1, wherein the step of polishing the first polysilicon layer is performed by a chemical-mechanical polishing utilizing a polishing speed difference between the first polysilicon layer and the first oxide layer.
Claim 6
Independent Claim
286 words
A method for fabricating a pillar bipolar transistor, the method comprising the steps of: etching a silicon substrate of a first conductivity type using a first patterned insulating layer as a mask to form a first and a second pillar structures separated by a trench region therein; injecting an impurity of a second conductivity type using a second patterned insulating layer as a mask to form an emitter region under the first and second pillar structures and in the second pillar structure; sequentially depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base region; etching the first oxide layer formed on both sides of the first pillar structure to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; sequentially depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed on or over the first pillar structure to expose a surface of the first pillar structure; injecting an impurity of the first conductivity type in the first pillar structure to form a base region at a center portion thereof; injecting an impurity of the second conductivity type to form a collector region at an upper portion of the first pillar structure; depositing a third polysilicon layer on the collector region, the third polysilicon layer being formed wider than the collector region; and forming self-aligned contact holes to form electrodes.
Claim 7
Independent Claim
286 words
A method for fabricating a pillar bipolar transistor, the method comprising the steps of: etching a silicon substrate of a first conductivity type using a first patterned insulating layer as a mask to form a first and a second pillar structures separated by a trench region therein; injecting an impurity of a second conductivity type using a second patterned insulating layer as a mask to form an emitter region under the first and second pillar structures and in the second pillar structure; sequentially depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base region; etching the first oxide layer formed on both sides of the first pillar structure to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; sequentially depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed on or over the first pillar structure to expose a surface of the first pillar structure; injecting an impurity of the first conductivity type in the first pillar structure to form a base region at a center portion thereof; injecting an impurity of the second conductivity type to form a collector region at an upper portion of the first pillar structure; depositing a third polysilicon layer on the collector region, the third polysilicon layer being formed wider than the collector region; and forming self-aligned contact holes to form electrodes.
References Cited (Backward Citations)
US4157269A
Cited
US4378630A
Cited
US5061645A
Cited
EP0140369A1
Cited
US4764001A
Cited
US4693782A
Cited
US4849371A
Cited
JPS63215068A
Cited
US4969026A
Cited
US4965217A
Cited
JPH0536712A
Cited
US5409845A
Cited
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