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US5504855A
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Method and apparatus for providing fast multi-color storage in a frame buffer
Assignee: Samsung Semiconductor Inc
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Filing: 1993-10-29
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Granted: 1996-04-02
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Expires: 2013-10-29
Abstract
Abstract A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.
Inventors
- 👤 Curtis Priem
- 👤 Chris Malachowsky
- 👤 Rick Silverman
- 👤 Shuen C. Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:14
CPC Classifications
G; G06; G06F; G06F15/00; G09; G09G; G09G5/00; G09G5/02; G09G5/022; G09G5/36; G09G5/39; G09G5/393; G11; G11C; G11C7/00; G11C7/10; G11C7/1078
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
90 words
A computer system comprising a central processing unit, main memory, a busing system including a data bus, an output display, and a frame buffer joining the busing system to the output display, the frame buffer comprising an array of memory cells for storing data indicating pixels to be displayed on the output display, access circuitry for selecting memory cells in the array, first and second color value registers, and circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously.
Claim 2
Dependent Claim
90 words
A computer system comprising a central processing unit, main memory, a busing system including a data bus, an output display, and a frame buffer joining the busing system to the output display, the frame buffer comprising an array of memory cells for storing data indicating pixels to be displayed on the output display, access circuitry for selecting memory cells in the array, first and second color value registers, and circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously.
Claim 3
Dependent Claim
72 words
A computer system as claimed in claim 1 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and a source of control signals for causing the multiplexors to select color values from the color registers and from the data bus.
Claim 4
Dependent Claim
39 words
A computer system as claimed in claim 2 in which the circuitry for causing the multiplexors to select color values from the color registers and from the data bus comprises circuitry for transferring control signals on the data bus.
Claim 5
Dependent Claim
53 words
A computer system as claimed in claim 1 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously includes circuitry connected for writing from a single color value register to a plurality of storage positions in the array simultaneously.
Claim 6
Dependent Claim
71 words
A computer system as claimed in claim 4 in which the circuitry connected for writing from a single color value register to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and circuitry for transferring control signals to cause the multiplexors to select color values from the color registers and from the data bus.
Claim 7
Dependent Claim
52 words
A computer system as claimed in claim 1 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously includes circuitry connected for writing from both color value registers to a plurality of storage positions in the array simultaneously.
Claim 8
Dependent Claim
69 words
A computer system as claimed in claim 6 in which the circuitry for writing from both color value registers to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and circuitry for transferring control signals to cause the multiplexors to select color values from the color registers and from the data bus.
Claim 9
Dependent Claim
80 words
A computer system as claimed in claim 1 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously includes means for writing from a single color value register to a plurality of storage positions in the array simultaneously, and circuitry for transferring control signals to cause color values to be written from both color value registers to a plurality of storage positions in the array simultaneously.
Claim 10
Dependent Claim
78 words
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer comprising an array of memory cells for storing data indicating pixels to be displayed on the output display, access circuitry for selecting memory cells in the array, first and second color value registers, and circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously.
Claim 11
Dependent Claim
78 words
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer comprising an array of memory cells for storing data indicating pixels to be displayed on the output display, access circuitry for selecting memory cells in the array, first and second color value registers, and circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously.
Claim 12
Dependent Claim
72 words
A frame buffer as claimed in claim 9 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and a source of control signals for causing the multiplexors to select color values from the color registers and from the data bus.
Claim 13
Dependent Claim
39 words
A frame buffer as claimed in claim 10 in which the means for causing the multiplexors to select color values from the color registers and from the data bus comprises circuitry for transferring control signals on the data bus.
Claim 14
Dependent Claim
53 words
A frame buffer as claimed in claim 9 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously comprises circuitry connected for writing from a single color value register to a plurality of storage positions in the array simultaneously.
Claim 15
Dependent Claim
71 words
A frame buffer as claimed in claim 12 in which the circuitry connected for writing from a single color value register to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and circuitry for transferring control signals to cause the multiplexors to select color values from the color registers and from the data bus.
Claim 16
Dependent Claim
52 words
A frame buffer as claimed in claim 9 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously comprises circuitry connected for writing from both color value registers to a plurality of storage positions in the array simultaneously.
Claim 17
Dependent Claim
70 words
A frame buffer as claimed in claim 14 in which the circuitry connected for writing from both color value registers to a plurality of storage positions in the array simultaneously comprises a plurality of multiplexors connected to each of the color registers and to the data bus, and circuitry for transferring control signals to cause the multiplexors to select color values from the color registers and from the data bus.
Claim 18
Dependent Claim
71 words
A frame buffer as claimed in claim 9 in which the circuitry for writing color value data from the color value registers to a plurality of storage positions in the array simultaneously comprises means for writing from a single color value register to a plurality of storage positions in the array simultaneously, and means for writing from both color value registers to a plurality of storage positions in the array simultaneously.
Claim 19
Independent Claim
62 words
A method for writing to a frame buffer including an array of memory cells comprising the steps of writing a first color value to a first color value register of the frame buffer, writing a second color value to a second color value register of the frame buffer, and selecting a color value to write to a plurality of memory cells simultaneously.
Claim 20
Independent Claim
62 words
A method for writing to a frame buffer including an array of memory cells comprising the steps of writing a first color value to a first color value register of the frame buffer, writing a second color value to a second color value register of the frame buffer, and selecting a color value to write to a plurality of memory cells simultaneously.
Claim 21
Dependent Claim
40 words
A method for writing to a frame buffer as claimed in claim 17 further comprising the step of selecting another color value to write to a plurality of memory cells simultaneously without the need to reload a color value register.
Claim 22
Dependent Claim
48 words
A method for writing to a frame buffer as claimed in claim 17 in which the step of selecting a color value to write to a plurality of memory cells simultaneously comprises selecting two color values to write to different ones of a plurality of memory cells simultaneously.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |