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US5504751A
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Method and apparatus for extracting digital information from an asynchronous data stream
Assignee: Apple Inc
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Filing: 1994-11-07
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Granted: 1996-04-02
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Expires: 2014-11-07
Abstract
Abstract A method and apparatus for extracting digital information (111) from an asynchronous data stream (101) is achieved by providing a data stream (101) that is clocked at a data stream clock rate (210). A sampled data stream (103) is produced by sampling the asynchronous data stream at a first clock rate (105), which is independent of the data stream clock rate (210). Using the sampled data stream (103), a recovered clock (107) is generated. The recovered clock (107) is then used to extract the digital information (111) from the sampled data stream (103).
Inventors
- 👤 Robert C. Ledzius
- 👤 James S. Irwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:22
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/10009; G11B20/10037; H; H04; H04L; H04L7/00; H04L7/02; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/4302; H04N21/4305; H04L7/0079; H04L7/0083; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
254 words
An asynchronous data extraction apparatus comprising: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal, the data stream clock recovery element including: an edge detector that detects edges in the sampled data stream to produce detected edges; a missing edge detector operably coupled to the edge detector, wherein the missing edge detector produces an injected edge when the edge detector does not produce one of the detected edges within a predetermined amount of time; and a clock generator coupled to the edge detector and the missing edge detector, wherein the clock generator combines the detected edges and the injected edge to produce the first representation of the data stream clock; and a data extraction element operably coupled to the data interface and the data stream clock recovery element, wherein the data extraction element extracts the digital information using the first representation of the data stream clock.
Claim 2
Dependent Claim
254 words
An asynchronous data extraction apparatus comprising: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal, the data stream clock recovery element including: an edge detector that detects edges in the sampled data stream to produce detected edges; a missing edge detector operably coupled to the edge detector, wherein the missing edge detector produces an injected edge when the edge detector does not produce one of the detected edges within a predetermined amount of time; and a clock generator coupled to the edge detector and the missing edge detector, wherein the clock generator combines the detected edges and the injected edge to produce the first representation of the data stream clock; and a data extraction element operably coupled to the data interface and the data stream clock recovery element, wherein the data extraction element extracts the digital information using the first representation of the data stream clock.
Claim 3
Dependent Claim
16 words
The asynchronous data extraction apparatus of claim 1, wherein the missing edge detector comprises a counter.
Claim 4
Dependent Claim
219 words
A digital-to-analog converter comprising: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal; a data extraction element operably coupled to the data interface and the clock recovery element, wherein the data extraction element extracts the digital information at the first representation of the data stream clock to produce extracted data; a sigma-delta converter that is operably coupled to the data extraction element, wherein the sigma-delta converter converts, at a rate representative of the first clock signal, the extracted data into a single bit stream; and a low pass filter that is operably coupled to the sigma-delta converter, wherein the low pass filter converts the single bit stream into an analog signal.
Claim 5
Dependent Claim
219 words
A digital-to-analog converter comprising: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal; a data extraction element operably coupled to the data interface and the clock recovery element, wherein the data extraction element extracts the digital information at the first representation of the data stream clock to produce extracted data; a sigma-delta converter that is operably coupled to the data extraction element, wherein the sigma-delta converter converts, at a rate representative of the first clock signal, the extracted data into a single bit stream; and a low pass filter that is operably coupled to the sigma-delta converter, wherein the low pass filter converts the single bit stream into an analog signal.
Claim 6
Dependent Claim
43 words
The digital-to-analog converter of claim 3, wherein the data extraction element further comprises a preamble detector, wherein the preamble detector monitors the sampled data stream and produces a preamble detect output when a preamble bit sequence is detected in the sampled bit stream.
Claim 7
Dependent Claim
36 words
The digital-to-analog converter of claim 3, wherein the data extraction element further comprises a shift register, wherein the shift register converts a least-significant-bit-first representation of the digital information to a most-significant-bit-first representation of the digital information.
Claim 8
Dependent Claim
36 words
The digital-to-analog converter of claim 3, wherein the data extraction element further comprises a shift register, wherein the shift register converts a serial representation of the digital information to a parallel representation of the digital information.
Claim 9
Dependent Claim
39 words
The digital-to-analog converter of claim 3 further comprises a clock divider operably coupled to the first clock, wherein the clock divider divides the first clock signal by a divisor to produce the rate representative of the first clock signal.
Claim 10
Dependent Claim
44 words
The digital-to-analog converter of claim 3 further comprises a finite impulse response filter operably coupled to the data extraction element, the sigma-delta converter, and the data stream clock recovery element wherein the finite impulse response filter filters, based on predetermined coefficients, the extracted data.
Claim 11
Dependent Claim
224 words
An integrated circuit comprising: a substrate having deposited thereon: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal; a data extraction element operably coupled to the data interface and the clock recovery element, wherein the data extraction element extracts the digital information at the first representation of the data stream clock to produce extracted data; a sigma-delta converter that is operably coupled to the data extraction element, wherein the sigma-delta converter converts, at a rate representative of the first clock signal, the extracted data into a single bit stream; and a low pass filter that is operably coupled to the sigma-delta converter, wherein the low pass filter converts the single bit stream into an analog signal.
Claim 12
Dependent Claim
224 words
An integrated circuit comprising: a substrate having deposited thereon: a first clock that provides a first clock signal having a first clock rate; a data interface that samples a data stream at the first clock rate to produce a sampled data stream, wherein digital information of the data stream is formatted using a data stream clock, and wherein the first clock signal is not synchronized with the data stream clock; a data stream clock recovery element that is operably coupled to the data interface and the first clock, wherein the data stream clock recovery element recovers a first representation of the data stream clock from the sampled data stream and wherein the first representation of the data stream clock is synchronous to the first clock signal; a data extraction element operably coupled to the data interface and the clock recovery element, wherein the data extraction element extracts the digital information at the first representation of the data stream clock to produce extracted data; a sigma-delta converter that is operably coupled to the data extraction element, wherein the sigma-delta converter converts, at a rate representative of the first clock signal, the extracted data into a single bit stream; and a low pass filter that is operably coupled to the sigma-delta converter, wherein the low pass filter converts the single bit stream into an analog signal.
Claim 13
Independent Claim
146 words
A method for extracting asynchronous data, the method comprises the steps of: receiving a data stream, wherein digital information of the data stream is formatted using a data stream clock; sampling the data stream at a first clock rate to produce a sampled data stream, wherein the first clock rate is independent of the data stream clock rate; detecting edges in the sampled data stream to produce detected edges; monitoring the detected edges and producing an injected edge when one the detected edges is not produced within a predetermined amount of time; and combining the detected edges and the injected edge to produce the first representation of the data stream clock, wherein the first representation of the data stream clock is synchronous to the first clock signal; and extracting the digital information from the sampled data stream at the first representation of the data stream clock.
Claim 14
Independent Claim
146 words
A method for extracting asynchronous data, the method comprises the steps of: receiving a data stream, wherein digital information of the data stream is formatted using a data stream clock; sampling the data stream at a first clock rate to produce a sampled data stream, wherein the first clock rate is independent of the data stream clock rate; detecting edges in the sampled data stream to produce detected edges; monitoring the detected edges and producing an injected edge when one the detected edges is not produced within a predetermined amount of time; and combining the detected edges and the injected edge to produce the first representation of the data stream clock, wherein the first representation of the data stream clock is synchronous to the first clock signal; and extracting the digital information from the sampled data stream at the first representation of the data stream clock.
Claim 15
Dependent Claim
20 words
The method of claim 10 further comprises manipulating the digital information at a rate representative of the first clock rate.
Claim 16
Dependent Claim
30 words
The method of claim 11, wherein manipulating the digital information further comprises dividing the first clock rate by a divisor to produce the rate representative of the first clock rate.
Claim 17
Dependent Claim
25 words
The method of claim 11, wherein extracting the digital information further comprises extracting a frame synchronizing signal which is used in manipulating the digital information.
Claim 18
Independent Claim
144 words
A method for converting a digital signal to an analog signal, the method comprises the steps of: receiving a data stream, wherein digital information of the data stream is formatted using a data stream clock; sampling the data stream at a first clock rate to produce a sampled data stream, wherein the first clock rate is independent of the data stream clock; recovering a first representation of the data stream clock from the sampled data stream, wherein the first representation of the data stream clock is synchronous to the first clock rate; extracting the digital information from the sampled data stream at the first representation of the data stream clock; generating, from the digital information, a single bit stream at a rate representative of the first clock rate; and filtering the single bit stream to convert the single bit stream into an analog signal.
Claim 19
Independent Claim
144 words
A method for converting a digital signal to an analog signal, the method comprises the steps of: receiving a data stream, wherein digital information of the data stream is formatted using a data stream clock; sampling the data stream at a first clock rate to produce a sampled data stream, wherein the first clock rate is independent of the data stream clock; recovering a first representation of the data stream clock from the sampled data stream, wherein the first representation of the data stream clock is synchronous to the first clock rate; extracting the digital information from the sampled data stream at the first representation of the data stream clock; generating, from the digital information, a single bit stream at a rate representative of the first clock rate; and filtering the single bit stream to convert the single bit stream into an analog signal.
Claim 20
Dependent Claim
34 words
The method of claim 14, wherein the step of extracting the digital information further comprises monitoring the sampled data stream and producing a preamble detect output when a predetermined preamble bit sequence is detected.
Claim 21
Dependent Claim
31 words
The method of claim 14, wherein the step of extracting the digital information further comprises converting a least-significant-bit-first representation of the digital information to a most-significant-bit-first representation of the digital information.
Claim 22
Dependent Claim
31 words
The method of claim 14, wherein the step of extracting the digital information further comprises converting a serial representation of the digital information to a parallel representation of the digital information.
Claim 23
Dependent Claim
25 words
The method of claim 14 further comprises dividing the first clock rate by a divisor to produce the rate representative of the first clock rate.
Claim 24
Dependent Claim
23 words
The method of claim 14, further comprises, prior to the generating a single bit stream step, filtering the digital information using predetermined coefficients.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |