Data interfacing method and its device

Claim 2

A data interfacing device receiving asynchronous serial data of a predetermined format, said format being a predetermined data group composed of a number of data lines, each consisting of multiple data bits, and receiving a basic clock signal; said data interfacing device providing synchronism to said asynchronous serial data and comprising: means responsive to said asynchronous serial data having a start bit at the start of said each data line for generating a line recognizing signal for recognizing a section of each data line; means for responsive to said basic clock and said line recognizing signal for generating a line clock signal having a predetermined pulse occurring at an ending time point synchronized to the end of each data line; means responsive to said line recognizing signal for generating a group clock signal having a predetermined pulse occurring at an ending time point synchronized to the end of each said data group; and means responsive to said basic clock signal and said line recognizing signal for generating a synchronizing clock signal for synchronizing each data bit of said data group.

Claim 3

A data interfacing device as defined in claim 1, further comprising a data extracting means for extracting data responsive to said synchronizing clock signal and said asynchronous serial data thereby extracting selected data bits from said data group.

Claim 4

A data interfacing device as claimed in claim 1, wherein said line recognizing signal generating means comprises: a logic circuit for receiving said asynchronous serial data and said line clock signal and generating a signal having a predetermined pulse at the start bit of each data line; and a flipflop responsive to an output signal of said logic circuit and to said line clock signal for providing said line recognizing signal having a continuous logic level during each data line section.

Claim 5

A data interfacing device as claimed in claim 3, wherein said logic circuit is an AND gate which receives said asynchronous serial data and said line clock signal and generates a pulse signal of a predetermined period having a pulse of a high logic level during a respective start bit section.

Claim 6

A data interfacing device as claimed in claim 3, wherein said flipflop is a JK-flipflop in which a logic `O` is applied to the `J` and `K` input terminals, the output signal of said AND gate is applied to a preset terminal, said line clock signal is applied to a clear terminal, and which has a start bit pulse signal having a pulse of high level from said start bit of each said data line applied to a clock terminal thereof.

Claim 7

A data interfacing device as claimed in claim 4, wherein said flipflop is a JK-flipflop in which a logic `O` is applied to the `J` and a `K` input terminals, the output signal of said AND gate is applied to a preset terminal, said line clock signal is applied to a clear terminal, and which has a start bit pulse signal having a pulse of high level from said start bit of each said data line applied to a clock terminal thereof.

Claim 8

A data interfacing device as claimed in claim 1, wherein said line clock signal generating means comprises: a counter responsive to said line recognizing signal being applied to a clear terminal thereof for counting said basic clock signal applied to a clock terminal thereof; a logic section connected to an output of said counter for providing a logic output signal when the count in said counter corresponds to the number of basic clock pulses corresponding to a line of data; and a flipflop for receiving the logic output signal of said logic section and said basic clock signal for providing line clock signal.

Claim 9

A data interfacing device as claimed in claim 7, wherein said counter comprises a number of counter stages, each of which has said line recognizing signal applied to its clear terminal and said basic clock signal applied to its clock terminal.

Claim 10

A data interfacing device as claimed in claim 8, wherein said logic section comprises: a plurality of logic elements for receiving respectively counting data outputted from said counter stages and outputting a logic `1` when the count data applied thereto is at a respective predetermined value; and an AND gate for receiving the output data from said logic elements and outputting a logic `1` when said logic elements output all logic `1s`.

Claim 11

A data interfacing device as claimed in claim 7, wherein said flipflop is a D-flipflop in which said logic output signal of said logic section is applied to a data input terminal, said basic clock signal is applied to a clock terminal, and which generates a high level pulse having a pulse section corresponding to a predetermined number of pulse sections of said basic clock signal at an ending time point of each said data line.

Claim 12

A data interfacing device as claimed in claim 1, wherein said group clock signal generating means comprises: a counter responsive to said line recognizing signal being applied to a clock terminal therefor for executing a counting operation; a first logic section for outputting a predetermined logic signal when the count accumulated by said counter coincides with the number of data lines in said data group; and a second logic section receiving an output signal of said first logic section and said line recognizing signal, for generating a group clock signal having a predetermined pulse at a time corresponding to the end of said data group.

Claim 13

A data interfacing device as claimed in claim 11, wherein said counter is reset to a predetermined value by said group clock signal from said second logic section.

Claim 14

A data interfacing device as claimed in claim 11, wherein said second logic section comprises: a D-flipflop in which the output signal of said first logic section is input to a data input terminal thereof, and an inverted signal of said line recognizing signal is inputted to a clock terminal thereof, and which generates a pulse signal having a high level during one data line section; and a logic element receiving an output signal of said D-flipflop and said output signal of said first logic section for generating said group clock signal.

Claim 15

A data interfacing device as claimed in claim 1, wherein said synchronizing clock signal generating means comprises: a counter responsive to said line recognizing signal applied to a clear terminal thereof for counting said basic clock signal applied to a clock terminal thereof; and a logic section for receiving count data output from said counter for generating a synchronizing signal having a period corresponding to a single data bit section of said asynchronous serial data.

Claim 16

A data interfacing device as claimed in claim 14, wherein said logic section comprises: a logic element for receiving said count data output from said counter and for outputting a logical output of `1` when said count data is at a value corresponding to `1/2` of said `1` data bit section; and a JK-flipflop having a logical output of said logic element applied to its `J` and `K` terminals and having said basic clock signal applied to a clock terminal thereof, and outputting said synchronizing clock signal.

Claim 17

A data interfacing means as claimed in claim 14, wherein said logic section comprises a logic element and wherein said counter is reset to a predetermined value by a logic signal output from the logic element of said logic section.

Claim 18

A data interfacing means as claimed in claim 15, wherein said counter is reset to a predetermined value by said logical output from the logic element of said logic section.

Claim 19

A data interfacing device as claimed in claim 2, wherein said data extracting means comprises a plurality of shift registers for storing said asynchronous serial data of said data group clocked therein under control of said synchronizing clock signal.

Claim 20

A data interfacing device as claimed in claim 18, wherein said shift registers are connected in series and said asynchronous serial data of said data group is input to a data input terminal of the first of said shift registers and said synchronizing clock signal is input to a clock terminal of said first shift register and the output of each said shift register of a prior stage is applied to an input of the shift register of the next stage.

Claim 21

In a data interfacing method which has a predetermined data format, receives serial asynchronous data of a predetermined magnitude comprising a data group made up of a number of data lines each consisting of a multiplicity of data sections, said data interfacing method using a pulse signal having a predetermined frequency as a basic clock signal for providing a predetermined synchronism to said data group; said data interfacing method comprising the steps of: receiving in series said asynchronous data of the data group including a start bit indicating the start of each said data line and generating a line recognizing signal for each data line; generating a line clock signal having a predetermined pulse at end time point of each said data line responsive to said basic clock signal and said line recognizing signal; generating a group clock signal having a predetermined pulse at end time point of said data group responsive to said line recognizing signal; and generating a synchronizing clock signal for synchronizing each data bit of said data group responsive to said basic clock signal and said line recognizing signal.

Claim 22

In a data interfacing method which has a predetermined data format, receives serial asynchronous data of a predetermined magnitude comprising a data group made up of a number of data lines each consisting of a multiplicity of data sections, said data interfacing method using a pulse signal having a predetermined frequency as a basic clock signal for providing a predetermined synchronism to said data group; said data interfacing method comprising the steps of: receiving in series said asynchronous data of the data group including a start bit indicating the start of each said data line and generating a line recognizing signal for each data line; generating a line clock signal having a predetermined pulse at end time point of each said data line responsive to said basic clock signal and said line recognizing signal; generating a group clock signal having a predetermined pulse at end time point of said data group responsive to said line recognizing signal; and generating a synchronizing clock signal for synchronizing each data bit of said data group responsive to said basic clock signal and said line recognizing signal.

Claim 23

A method as claimed in claim 20, further comprising extracting particular data from said data group by using said synchronizing clock signal obtained from said synchronizing clock signal generating step.

Claim 24

A method as claimed in claim 20, wherein said line clock signal generating step comprises: counting said basic clock signal during the data line section of said line recognizing signal; and generating said line clock signal having a predetermined pulse at the termination of the count during each said data line section.

Claim 25

A method as claimed in claim 20, wherein said group clock signal generating step comprises: counting the number of said data lines by using said line recognizing signal as a clock; and generating said group clock signal having a predetermined pulse at the termination of the count of the final data line of said data group.

Claim 26

A method as claimed in claim 20, wherein said synchronizing clock signal generating step comprises: counting the clocks of said basic clock signal during the data line of said line recognizing signal; and generating a clock signal having a period corresponding to the period of each data bit of said data group.

Claim 27

A method as claimed in claim 21, wherein said data extracting step comprises: applying said data of said data group in series to serial connected shift registers; clocking said data into the first stage of said shift registers under timing control of said synchronizing clocks; and shifting said data serially through said shift registers under the time control of said synchronizing clocks.