Message routing

Claim 2

A communications routing device for routing messages between a plurality of input channels and a plurality of output channels, comprising: routing means for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices, each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a single selected memory device of said plurality of memory devices, to generate a single address signal dependent upon said content of said received message, to supply said address signal to the address port of only said selected memory device, and to supply said stored routing data from the data port of said selected memory device to said routing means.

Claim 3

A communications routing device as claimed in claim 1, in which each said memory device further comprises a data input port, and further comprising altering means, connected to the address ports and the data input ports of said plurality of memory devices, for selectively altering the stored routing data stored in said memory devices.

Claim 4

A communications routing device as claimed in claim 2 in which the altering means is connected to said access circuit, via which it is connected to said address ports.

Claim 5

A communications routing device as claimed in claim 1, in which the received message comprises a header portion and a data portion, and in which the access circuit is responsive to the header portion to select said memory device and to generate said address signal.

Claim 6

A communications routing device as claimed in claim 4 in which said stored routing data specifies said first output channel.

Claim 7

A communications routing device as claimed in claim 4 in which said stored routing data comprises substitute header data, and in which said access circuit further comprises combining means, connected to said data ports, for combining said substitute header data with the data portion of said received message.

Claim 8

A communications routing device as claimed in claim 6, in which said routing means is connected between said combining means and said output channels.

Claim 9

A communications routing device as claimed in claim 1, further comprising a plurality of channel receivers coupled to said input channels and to said access circuit.

Claim 10

A communications routing device as claimed in claim 8, in which said channel receivers are ATM receivers and said messages are ATM cells.

Claim 11

A communications routing device as claimed in claim 8, in which said channel receivers are optical receivers.

Claim 12

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices., each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a single selected memory device of said plurality of memory devices, to generate a single address signal dependent upon said content of said received message, and to supply said address signal to the address port of said selected memory device, in which the received message comprises a header portion and a data portion, and in which the access circuit is responsive to the header portion to select said memory device and to generate said address signal, and in which said stored routing data comprises substitute header data, and further comprising combining means, connected to said data ports, for combining said substitute header data with the data portion of said received message, and in which said access circuit comprises an inward routing network connected between said input channels and said address ports, for routing at least said header portion to said selected memory device.

Claim 13

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices., each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a single selected memory device of said plurality of memory devices, to generate a single address signal dependent upon said content of said received message, and to supply said address signal to the address port of said selected memory device, in which the received message comprises a header portion and a data portion, and in which the access circuit is responsive to the header portion to select said memory device and to generate said address signal, and in which said stored routing data comprises substitute header data, and further comprising combining means, connected to said data ports, for combining said substitute header data with the data portion of said received message, and in which said access circuit comprises an inward routing network connected between said input channels and said address ports, for routing at least said header portion to said selected memory device.

Claim 14

A communications routing device as claimed in claim 11, in which said inward routing network also routes said data portion, and said combining means comprise a plurality of combining circuits, each associated with one of said memory device.

Claim 15

A communications routing device as claimed in claim 11, in which said access circuit further comprises a further routing network, and said combining means comprises a plurality of combining circuits, and said further routing network connects said data ports with said combining circuits.

Claim 16

A communications routing device as claimed in claim 13, in which said inward routing network comprises a plurality of inward paths, and said further routing network comprises a plurality of outward paths, and further comprising a plurality of routing nodes for selectively interconnecting a plurality of said inward paths, said nodes also selectively interconnecting said outward paths.

Claim 17

A communications routing device as claimed in claim 13, in which said inward routing network comprises a plurality of inward paths, and said further routing network comprises a plurality of outward paths, and in which said access circuit further comprises a plurality of inward routing nodes for selectively interconnecting a plurality of said inward paths, a plurality of outward routing nodes for selectively interconnecting said outward paths, and a control circuit for jointly controlling said inward nodes and said outward nodes, in dependence upon said header portion.

Claim 18

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: a routing device for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices, each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory device being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a selected memory device of said plurality of memory devices, to generate an address signal dependent upon said content of said received message, and to supply said address signal to the address port of said selected memory device, in which said access circuit comprises an inward routing network connected between said input channel and said address input ports for routing said address signal to said selected memory device in accordance with control data, and a control circuit for generating said control data dependent upon said content of said received message.

Claim 19

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: a routing device for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices, each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory device being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a selected memory device of said plurality of memory devices, to generate an address signal dependent upon said content of said received message, and to supply said address signal to the address port of said selected memory device, in which said access circuit comprises an inward routing network connected between said input channel and said address input ports for routing said address signal to said selected memory device in accordance with control data, and a control circuit for generating said control data dependent upon said content of said received message.

Claim 20

A communications circuit as claimed in claim 16, in which said access circuit comprises means for prefixing said control data as a prefix to said address signal, and said inward routing network is responsive to said prefix to route said address signal.

Claim 21

A communications routing device as claimed in claim 16, in which said control circuit also generates said address signal.

Claim 22

A communications routing device as claimed in claim 16, in which said received message comprises a routing portion, and said control device applies a function to said routing portion to generate said control data.

Claim 23

A communications routing device as claimed in claim 19, in which said function is such that, over time, for messages received from each said input channel, said access circuit will access in sequence, all of said memory devices.

Claim 24

A communications routing device as claimed in claim 19, in which said function is a linear modulo-N function.

Claim 25

A communications routing device as claimed in claim 19, in which said routing portion comprises an address lying in an address sequence, and the function is such as to distribute successive addresses of said sequence successively between said memory devices.

Claim 26

A communications routing device as claimed in claim 19, further comprising means for changing said function.

Claim 27

A communications routing device as claimed in claim 19, further comprising means for changing said function.

Claim 30

A method as claimed in claim 25, further comprising the step of controlling said routing device in accordance with said routing data.

Claim 31

A method as claimed in claim 25, further comprising the step of modifying said received message in accordance with said routing data, to modify subsequent routing of said received message.

Claim 32

The method of claim 25, in which said received message is an ATM cell and said communications routing device is an ATM routing node.

Claim 33

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices, each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a single selected memory device of said plurality of memory devices, to generate an address signal dependent upon said content of said message, to supply said address signal to the address port of said selected memory device and to supply said stored routing data from the data port of said selected memory device to said routing means in which said access circuit comprises an inward routing network connected between said input channels and said address ports for routing said address signal to said selected memory device in accordance with control data, and an address distributing circuit for generating said control data dependent upon said content of said message.

Claim 34

A communications routing device for routing messages between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received message from a first input channel to a first output channel in dependence upon routing data; a plurality of memory devices, each containing stored routing data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored routing data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the content of said received message, to select a single selected memory device of said plurality of memory devices, to generate an address signal dependent upon said content of said message, to supply said address signal to the address port of said selected memory device and to supply said stored routing data from the data port of said selected memory device to said routing means in which said access circuit comprises an inward routing network connected between said input channels and said address ports for routing said address signal to said selected memory device in accordance with control data, and an address distributing circuit for generating said control data dependent upon said content of said message.

Claim 35

A communications routing device as claimed in claim 29, in which said access circuit comprises means for prefixing said control data as a prefix to said address signal, and said inward routing network is responsive to said prefix to route said address signal.

Claim 36

A communications routing device as claimed in claim 29, in which said address distributing circuit also generates said address signal.

Claim 37

A communications routing device as claimed in claim 29, in which said received message comprises a routing portion, and said address distributing circuit applies a function to said routing portion to generate said control data.

Claim 38

A communication routing device as claimed in claim 32, in which said function is such that, over time, for messages received from each said input channel, said access circuit will access in sequence, all of said memory devices.

Claim 39

A communications routing device as claimed in claim 32, in which said function is a linear modulo-N function.

Claim 40

A communications routing device as claimed in claim 32, in which said routing portion comprises an address lying in an address sequence, and the function is such as to distribute successive addresses of said sequence successively between said memory devices.

Claim 41

An ATM routing node for routing ATM cells between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received ATM cell comprising a header portion and a data portion from a first input channel to a first output channel; and an ATM cell header replacement device comprising; a plurality of memory devices, each containing stored ATM cell header replacement data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored ATM cell header replacement data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the header of said received ATM cell, to select a single selected memory device of said plurality of memory devices, to generate an address signal dependent upon said header of said ATM cell, to supply said address signal to the address port of said selected memory device, and to combine said stored ATM cell header replacement data with said data portion; in which said access circuit comprises an inward routing network connected between said input channels and said address ports for routing said address signal to said selected memory device in accordance with control data, and an address distributing circuit for generating said control data dependent upon said header of said ATM cell.

Claim 42

An ATM routing node for routing ATM cells between a plurality of input channels and plurality of output channels, comprising: routing means for selectively routing a received ATM cell comprising a header portion and a data portion from a first input channel to a first output channel; and an ATM cell header replacement device comprising; a plurality of memory devices, each containing stored ATM cell header replacement data stored at corresponding addresses therein, each memory device comprising an address port for receiving an address signal corresponding to an address and a data port for outputting the stored ATM cell header replacement data stored at the address corresponding to said address signal, said memory devices being separately accessible in parallel; and an access circuit connected to the address ports of said plurality of memory devices and connected to said first input channel, said access circuit being operable, in response to the header of said received ATM cell, to select a single selected memory device of said plurality of memory devices, to generate an address signal dependent upon said header of said ATM cell, to supply said address signal to the address port of said selected memory device, and to combine said stored ATM cell header replacement data with said data portion; in which said access circuit comprises an inward routing network connected between said input channels and said address ports for routing said address signal to said selected memory device in accordance with control data, and an address distributing circuit for generating said control data dependent upon said header of said ATM cell.