EP0373299A2
Expired / Lapsed
EP
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Method and apparatus for memory routing scheme
Assignee: Pixar
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Filing: 1989-08-24
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Granted: —
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Expires: 2009-08-24
Abstract
Abstract A memory routing scheme for a computer system having M processors (P0 ... P5) and N memories is described. M processors are coupled through a randomizer (23) to a routing network (10), such as a crossbar. The crossbar is coupled to N memories (MEM 0 ... 5). When a memory address is specified by a processor, it is acted on by the randomizer and a routed address is given to the memory. The memory having the routed address is coupled to the processor for the access. By utilizing a random routing scheme, the memories are not optimized for any one particular access mode, but present the same look to the processors regardless of the access mode. The average number of collisions in this scheme is a function of the number of memories, number of processors and number of access ports. In one embodiment, a hashing table is utilized for the assignment of the routing address to the memories. Alternatively, a randomizing function is utilized to generate a routing address.
Inventors
- 👤 Mark Leather
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F12/06; G06F12/0607
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
69 words
A method for addressing a plurality of memory locations in a multiple processing environment comprising the steps of: generating a memory address at each of a plurality of processors; providing said memory address to a randomizing means, converting said memory address to a random address; providing said random address to a routing means coupling said each processor to a memory corresponding to said random address through said routing means.
Claim 2
Independent Claim
69 words
A method for addressing a plurality of memory locations in a multiple processing environment comprising the steps of: generating a memory address at each of a plurality of processors; providing said memory address to a randomizing means, converting said memory address to a random address; providing said random address to a routing means coupling said each processor to a memory corresponding to said random address through said routing means.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said routing means comprises a crossbar.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein said randomizing means comprises a hash table.
Claim 5
Dependent Claim
41 words
The method of claim 3 wherein said hash table comprises a plurality of look up tables, each of said look up tables having an equal number of inputs and outputs, said hash table having an equal number of inputs and outputs.
Claim 6
Dependent Claim
138 words
A circuit comprising: a plurality of processors (P0 ... P5) a plurality of randomizing means (23), each randomizing means coupled to one of said plurality of said processors; a plurality of memories (MEM 0 ... MEM 5) coupled to said plurality of randomizing means through a routing circuit (10) such that each of said plurality of memories may be coupled to any of said plurality of randomizing means; each of said processors providing a memory address to each of said randomizing means, said randomizing means (23) converting said memory address to a random address; said randomizing means (23) providing said random address to said routing means (10) such that each of said processors (P0 ... P5) is coupled to one of said plurality of memories (MEM 0 ... 5) corresponding to said random address through said routing means.
Claim 7
Dependent Claim
138 words
A circuit comprising: a plurality of processors (P0 ... P5) a plurality of randomizing means (23), each randomizing means coupled to one of said plurality of said processors; a plurality of memories (MEM 0 ... MEM 5) coupled to said plurality of randomizing means through a routing circuit (10) such that each of said plurality of memories may be coupled to any of said plurality of randomizing means; each of said processors providing a memory address to each of said randomizing means, said randomizing means (23) converting said memory address to a random address; said randomizing means (23) providing said random address to said routing means (10) such that each of said processors (P0 ... P5) is coupled to one of said plurality of memories (MEM 0 ... 5) corresponding to said random address through said routing means.
Claim 8
Dependent Claim
14 words
The circuit of claim 5 wherein said routing means (10) comprises a crossbar circuit.
Claim 9
Dependent Claim
18 words
The circuit of claim 5 or 6 wherein said randomizing means (10) comprises a hash table (Fig. 4).
Claim 10
Dependent Claim
122 words
The circuit of claim 7 wherein said hash table (Fig. 4) comprises a plurality of look up tables, a first plurality of look up tables (25 ... 28) is coupled to said processing means (P0 ... P5), said first plurality of look up tables having a first plurality of outputs (A0 ... D0), said first plurality of outputs coupled to a second plurality of look up tables (29 ... 32), said second plurality of look up tables having a second plurality of outputs (A0 ... D0), said second plurality of outputs coupled to a third plurality of look up tables (33 ... 36), said third plurality of look up tables having a third plurality of outputs coupled to said routing means (10).
References Cited (Backward Citations)
No citation records indexed.
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