Method and apparatus for making corrections in a video monitor during horizontal scan

Claim 2

A circuit in a video monitor including a CRT, said circuit providing a variable adjustment of a selected parameter to adjust the selected parameter to be of a selected value during a horizontal scan of the CRT in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the selected parameter related to one of a plurality of display characteristics of the video monitor, the circuit comprising: a data storage device containing information of values representative of the selected value of the selected parameter; an integrator coupled to receive information signals representative of said information contained in said data storage device, said integrator for producing an integrated signal and for resetting the integrated signal produced thereat to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal; and an amplifier coupled to receive the integrated signal, said amplifier for applying amplified signals to the CRT in accordance with the integrated signal and the video signal.

Claim 3

A circuit as defined in claim 1, further comprising: a microcontroller in communication with said data storage device and adapted for manipulating said device to provide said information to said integrator.

Claim 4

A circuit as defined in claim 2 wherein said microcontroller can modify the information contained in said data storage device.

Claim 5

A circuit in a video monitor including a CRT, said circuit providing a variable adjustment of a selected parameter relating to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the circuit comprising: a data storage device containing information relating to a target value for the selected parameter; an integrator receptive of said information from said data storage device and adapted for producing an integrated signal therefrom and receptive of the horizontal sync signal and adapted for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal; and an amplifier receptive of the integrated signal and adapted for applying signals to the CRT in accordance with the integrated signal and the video signal; a pulse density modulator receptive of said information from said data storage device and adapted for generating a pulse density modulated signal relating to said information and supplying said modulated signal to said integrator; wherein said integrator is receptive of said pulse density modulated signal and produces said integrated signal therefrom.

Claim 6

A circuit in a video monitor including a CRT, said circuit providing a variable adjustment of a selected parameter relating to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the circuit comprising: a data storage device containing information relating to a target value for the selected parameter; an integrator receptive of said information from said data storage device and adapted for producing an integrated signal therefrom and receptive of the horizontal sync signal and adapted for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal; and an amplifier receptive of the integrated signal and adapted for applying signals to the CRT in accordance with the integrated signal and the video signal; a pulse density modulator receptive of said information from said data storage device and adapted for generating a pulse density modulated signal relating to said information and supplying said modulated signal to said integrator; wherein said integrator is receptive of said pulse density modulated signal and produces said integrated signal therefrom.

Claim 7

A circuit as defined in claim 4 wherein said information stored in said data storage device is divided into a plurality of discrete values, each discrete value corresponding to a selected value of the selected parameter for a predetermined segment of the horizontal scan of the CRT.

Claim 8

A circuit as defined in claim 5 wherein said plurality of discrete values constitutes a plurality in a range from sixteen to thirty-two discrete values per horizontal scan.

Claim 9

A circuit as defined in claim 4 wherein said pulse density modulator includes a tri-state gate coupled to receive the information signals representative of said information contained in said data storage device, said tri-state gate for providing said pulse density modulated signal, said modulated signal having three different levels with a first level causing the integrator to increase the level of the integrated signal, a second level causing the integrator to maintain the current level of the integrated signal, and a third level causing the integrator to decrease the level of the integrated signal.

Claim 10

A circuit as defined in claim 7 wherein said data storage device stores said information in a plurality of bytes, each byte containing a direction bit and a plurality of data bits, the direction bit being supplied to an input terminal of the tri-state gate and the data bits being sequentially applied to an enable terminal of the tri-state gate.

Claim 11

A circuit as defined in claim 8 wherein said pulse density modulator further includes a clock for generating a clock signal and a multiplexer receptive of the data bits of each selected byte from the data storage device and receptive of said clock signal, said multiplexer is adapted to provide each of the data bits sequentially at an output terminal in response to said clock signal, the output terminal of said multiplexer being connected to the enable terminal of said tri-state gate.

Claim 12

A circuit as defined in claim 9 wherein the frequency of the clock signal is the multiplicative product of the horizontal scan frequency, the number of bytes of information in the data storage device corresponding to the horizontal scan, and the number of data bits in each byte.

Claim 13

A circuit as defined in claim 10 wherein said pulse density modulator further includes a one-shot timer connected in-line between the output terminal of said multiplexer and the enable terminal of said tri-state gate.

Claim 14

A circuit in a video monitor including a CRT, said circuit providing a variable adjustment of a selected parameter relating to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the circuit comprising: a data storage device containing information of values representative of the selected value of the selected parameter; a first integrator receptive of said information from said data storage device and receptive of signals representative of the selected value of the selected parameter adapted for producing a first integrated signal therefrom and receptive of the horizontal sync signal and adapted for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal during horizontal scan; an amplifier receptive of the first integrated signal and adapted for applying signals to the CRT in accordance with the first integrated signal and the video signal a second integrator receptive of information of values representative of the selected value of the selected parameter for integration during a vertical scan of the CRT and adapted to produce a vertical-rate integrated signal therefrom; a third integrator receptive of information of values representative of the selected value of the display characteristic to which the selected parameter relates and adapted to produce a static integrated signal therefrom; and a summing circuit receptive of the first integrated signal, the vertical-rate integrated signal and the static integrated signal and adapted to produce a combined integrated signal which is supplied to said amplifier.

Claim 15

A circuit in a video monitor including a CRT, said circuit providing a variable adjustment of a selected parameter relating to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the circuit comprising: a data storage device containing information of values representative of the selected value of the selected parameter; a first integrator receptive of said information from said data storage device and receptive of signals representative of the selected value of the selected parameter adapted for producing a first integrated signal therefrom and receptive of the horizontal sync signal and adapted for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal during horizontal scan; an amplifier receptive of the first integrated signal and adapted for applying signals to the CRT in accordance with the first integrated signal and the video signal a second integrator receptive of information of values representative of the selected value of the selected parameter for integration during a vertical scan of the CRT and adapted to produce a vertical-rate integrated signal therefrom; a third integrator receptive of information of values representative of the selected value of the display characteristic to which the selected parameter relates and adapted to produce a static integrated signal therefrom; and a summing circuit receptive of the first integrated signal, the vertical-rate integrated signal and the static integrated signal and adapted to produce a combined integrated signal which is supplied to said amplifier.

Claim 16

A video monitor for receiving a video signal and generating a display image therefrom, the monitor providing automatic adjustment of a plurality of display characteristics via adjustment of selected parameters to adjust the selected parameters to be of selected values in response to a video signal including a horizontal sync signal, the selected parameters related to a plurality of display characteristics of the video monitor during a horizontal scan of the CRT, the monitor comprising: a CRT; a data storage device containing information of values representative of the selected value of the selected parameter; an integrator coupled to receive information signals representative of said information contained in said data storage device, said integrator for producing an integrated signal and for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal; and an amplifier coupled to receive the integrated signal, said amplifier for applying signals to the CRT in accordance with the integrated signal and the video signal.

Claim 17

A video monitor for receiving a video signal and generating a display image therefrom, the monitor providing automatic adjustment of a plurality of display characteristics via adjustment of selected parameters to adjust the selected parameters to be of selected values in response to a video signal including a horizontal sync signal, the selected parameters related to a plurality of display characteristics of the video monitor during a horizontal scan of the CRT, the monitor comprising: a CRT; a data storage device containing information of values representative of the selected value of the selected parameter; an integrator coupled to receive information signals representative of said information contained in said data storage device, said integrator for producing an integrated signal and for resetting the integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal; and an amplifier coupled to receive the integrated signal, said amplifier for applying signals to the CRT in accordance with the integrated signal and the video signal.

Claim 18

A video monitor as defined in claim 13, further comprising: a microcontroller in communication with said data storage device and adapted for manipulating said device to provide said information to said integrator.

Claim 19

A video monitor as defined in claim 14 wherein said microcontroller can modify the information contained in said data storage device.

Claim 20

A video monitor as defined in claim 13, further comprising: a pulse density modulator receptive of said information from said data storage device and adapted for generating a pulse density modulated signal relating to said information and supplying said modulated signal to said integrator; wherein said integrator is receptive of said pulse density modulated signal and produces said integrated signal therefrom.

Claim 21

A video monitor as defined in claim 16 wherein said information stored in said data storage device is divided into a plurality of discrete values, each discrete value corresponding to a target value for the given parameter for a predetermined segment of the horizontal scan of the CRT.

Claim 22

A video monitor as defined in claim 17 wherein said plurality of discrete values constitutes a plurality in a range from sixteen to thirty-two discrete values per horizontal scan.

Claim 23

A video monitor as defined in claim 16 wherein said pulse density modulator includes a tri-state gate coupled to receive information signals representative of said information contained in said data storage device and adapted to provide said pulse density modulated signal, said modulated signal having three different levels with a first level causing the integrator to increase the level of the integrated signal, a second level causing the integrator to maintain the current level of the integrated signal, and a third level causing the integrator to decrease the level of the integrated signal.

Claim 24

A video monitor as defined in claim 19 wherein said data storage device stores said information in a plurality of bytes, each byte containing a direction bit and a plurality of data bits, the direction bit being supplied to an input terminal of the tri-state gate and the data bits being sequentially applied to an enable terminal of the tri-state gate.

Claim 25

A video monitor as defined in claim 20 wherein said pulse density modulator further includes a clock for generating a clock signal and a multiplexer receptive of the data bits of each selected byte from the data storage device and receptive of said clock signal, said multiplexer is adapted to provide each of the data bits sequentially at an output terminal in response to said clock signal, the output terminal of said multiplexer being connected to the enable terminal of said tri-state gate.

Claim 26

A video monitor as defined in claim 21 wherein the frequency of the clock signal is the multiplicative product of the horizontal scan frequency, the number of bytes of information in the data storage device corresponding to the horizontal scan, and the number of data bits in-each byte.

Claim 27

A video monitor as defined in claim 22 wherein said pulse density modulator further includes a one-shot timer connected in-line between the output terminal of said multiplexer and the enable terminal of said tri-state gate.

Claim 28

A video monitor as defined in claim 13 wherein said integrator receives information relating to target values for the selected parameter for integration during horizontal scan and said video monitor further includes: a second integrator receptive of information relating to target values for the selected parameter for integration during a vertical scan of the CRT and adapted to produce a vertical-rate integrated signal therefrom; a third integrator receptive of information relating to a preselected value for the display characteristic to which the selected parameter relates and adapted to produce a static integrated signal therefrom; and a summing circuit receptive of the integrated signal, the vertical-rate integrated signal and the static integrated signal and adapted to produce a combined integrated signal which is supplied to said amplifier.

Claim 31

A method as defined in claim 25, further including the step of: resetting said integrated signal to a predetermined value upon recognition of a predetermined transition in the horizontal sync signal.

Claim 32

A method as defined in claim 25 wherein the storing step includes storing said information in an array and further wherein each row of information in the array is stored in a plurality of bytes, each byte including information relating to a predetermined segment of a predetermined group of horizontal scans.

Claim 33

A method as defined in claim 27 wherein each byte of information includes a plurality of bits, one bit being a direction bit and the remaining bits in each byte being data bits, said method further including the step of: creating a tri-state signal from the bytes of information, the direction bit determining the direction of the signal and the data bits sequentially providing the data as one of an upper level, an intermediate level, and a lower level depending upon the state of the direction bit.

Claim 34

A method as defined in claim 28 wherein the step of creating the tri-state signal includes maintaining a constant pulse width for the tri-state signal despite variations in the frequency of the horizontal sync signal.

Claim 35

A method as defined in claim 28 wherein the step of creating the tri-state signal includes the step of multiplexing the data bits to sequentially provide the data.

Claim 36

A method as defined in claim 30, further comprising the step of generating a clock signal at a frequency equal to the multiplicative product of the horizontal scan frequency, the number of bytes in a horizontal scan and the number of data bits in each byte, and wherein the clock signal is supplied to the multiplexer to control the sequential application of data.

Claim 37

A method as defined in claim 25, further including the step of integrating a static signal relating to a preselected value for the display characteristic; and wherein the summing step includes summing in the static integrated signal.

Claim 38

A circuit in a video monitor, said circuit providing a variable adjustment of a selected parameter to adjust the selected parameter to be of a selected value in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the selected parameter related to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT, the circuit comprising: a data storage device containing information of values representative of the selected value of the selected parameter; means operatively connected to the data storage device for creating a horizontal rate wave form from said stored information; and an amplifier coupled to receive the horizontal rate wave form, said amplifier for controlling the monitor in accordance with the horizontal rate wave form and the video signal.

Claim 39

A circuit in a video monitor, said circuit providing a variable adjustment of a selected parameter to adjust the selected parameter to be of a selected value in response to a video signal including a horizontal sync signal operating at a horizontal scan frequency, the selected parameter related to one of a plurality of display characteristics of the video monitor during a horizontal scan of the CRT, the circuit comprising: a data storage device containing information of values representative of the selected value of the selected parameter; means operatively connected to the data storage device for creating a horizontal rate wave form from said stored information; and an amplifier coupled to receive the horizontal rate wave form, said amplifier for controlling the monitor in accordance with the horizontal rate wave form and the video signal.

Claim 40

A circuit as defined in claim 33 wherein said information is stored in said data storage device in bytes with each byte containing information relating to the horizontal rate wave form for a predetermined segment of the horizontal scan.

Claim 41

A circuit as defined in claim 33 wherein said information is stored in said data storage device in a format such that each piece of stored information relates to the horizontal rate wave form for a predetermined pixel of the horizontal scan.