Method of low cost self-test in a video display system system

Claim 2

A display system with video analog self-test capability comprising: means, including a graphics processor, for generating digital video data; the processor having means for generating a variable duty cycle squarewave and having a digital input port; a digital to analog converter (DAC) for receiving the digital video data and converting the digital video data to an analog signal for input to a cathode ray tube monitor to display a graphics image; an integrator circuit for integrating said variable duty cycle squarewave; an analog comparator for comparing the analog signal to the integrated variable duty cycle squarewave; and means for connecting the output of said analog comparator to the digital input port.

Claim 3

The display system of claim 1 wherein said generating means includes three outputs to provide color digital video data to three DACs, and means for separately comparing the output of each DAC to the integrated squarewave.

Claim 4

The display system of claim 1, further comprising: a clock integrator for integrating the system clock signal; means for inputting the integrated system clock signal to the analog comparator; means for varying the duty cycle of the squarewave and thereby varying the output of the integrator until said output is equal to the integrated system clock signal; means in the processor for comparing the duty cycle of the squarewave, when the integrated squarewave equals the integrated system clock signal, to the duty cycle of the squarewave when the integrated squarewave is equal to the reference voltage; means in the processor for testing the output signal of said comparison means against predetermined limits to determine whether the clock is running; and means for reporting the result of said test.

Claim 5

The display system of claim 1, including: means for inputting a reference voltage to the comparator; and means in the processor for calibrating the variable duty cycle squarewave and the integral thereof against the reference voltage.

Claim 6

The display system of claim 4, including: means for varying the duty cycle of the square wave and thereby varying the output of the integrator until said output is equal to the output of the DAC; and means for comparing the duty cycle of the square wave, when the integrator output equals the output of the DAC, to the duty cycle of the square wave when calibrated against the reference voltage to measure the DAC output signal level.

Claim 7

The display system of claim 5, including: means for comparing the DAC output signal level to predetermined limits; and means for reporting the results of said comparison to a user.

Claim 10

The method of claim 7 wherein setting a DAC input comprises: generating digital test data; and outputting the digital test data to the DAC inputs.

Claim 11

The method of claim 7 further comprising providing an integrator connected to receive the system clock signal; and selecting the integrated system clock signal as the analog signal to be measured.

Claim 12

The method of claim 7 wherein said measuring comprises: initializing the system to bring the integrated binary signal level substantially equal to the DAC output voltage; determining a third value representative of the duty ratio of the binary signal; and calculating the analog signal level from the third value.

Claim 13

The method of claim 10 wherein said initializing comprises: (a) setting the binary signal to a logical high state; (b) integrating the binary signal; (c) comparing the integrated binary signal level to the DAC output voltage; (d) repeating steps (b) and (c) until the integrated binary signal level exceeds the DAC output voltage; (e) setting the binary signal to a logical low state; (f) integrating the binary signal; (g) comparing the integrated binary signal level to the DAC output voltage; (h) repeating steps (f) and (g) until the integrated binary signal level falls below the DAC output voltage.

Claim 15

The method of claim 10 wherein said calculating the analog signal level comprises dividing the third value by a predetermined number.

Claim 16

The method of claim 7, wherein the display system includes means for generating a binary signal, further comprising providing an integrator for integrating the binary signal; wherein said calibrating comprises: pretracking to bring the integrating binary signal voltage level substantially equal to the reference voltage; and executing a calibration loop to determine the duty ratio of the binary signal.

Claim 17

The method of claim 14 wherein said pretracking comprises: (a) setting the binary signal to a logical high state; (b) integrating the binary signal; (c) comparing the integrated binary signal level to the reference voltage; (d) repeating steps (b) and (c) until the integrated binary signal level exceeds the reference voltage; (e) setting the binary signal to a logical low state; (f) integrating the binary signal; (g) comparing the integrated binary signal level to the reference voltage; (h) repeating steps (f) and (g) until the integrated binary signal level falls below the reference voltage; (i) comparing the reference voltage to the integrated binary signal level; (j) setting the logical state of the binary signal in response to the comparison of step (i) so as to urge the integrated binary signal level toward the reference voltage; and (k) repeating steps (i) and (j) a predetermined number of times such that the memory effects of the integrator are dissipated.

Claim 18

The method of claim 14, further comprising providing an analog comparator connected to the integrator for receiving the integrated binary output signal; and wherein said graphics processor includes a digital input port for receiving the analog comparator output signals.

Claim 19

The method of claim 9, wherein executing the calibration loop comprises: multiplying the reference voltage by a predetermined number to determine a first value; and determining a second value such that the duty ratio of the binary signal is the ratio of the first value to the second value.

Claim 20

The method of claim 17, wherein said determining a second value comprises: (a) comparing the integrated binary signal level to the reference voltage; (b) setting the binary signal to a logical low state in response to the integrated binary signal level exceeding the reference voltage; (c) setting the binary signal to a logical high state in response to the reference voltage exceeding the integrated binary signal level; (d) counting the times the binary signal is set to a logical high state to determine a high count; (e) counting the times the binary signal is set to a logical low state to determine a low count; (f) repeating steps (a) through (e) until the high count equals the first value; and (g) summing the high count and the low count to determine the second value indicating the total number of times the calibration loop was executed.