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US5502730A
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Partial scan testability utilizing reconvergence through sequential elements
Assignee: NEC Corp
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Filing: 1994-06-10
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Granted: 1996-03-26
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Expires: 2014-06-10
Abstract
Abstract A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.
Inventors
- 👤 Rabindra K. Roy
- 👤 Toshinobu Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318586
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
88 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) finding reconvergence structures in the: circuit to be tested; (b) determining harmful reconvergence structures containing memory elements; (c) for each respective memory element in a harmful reconvergence structure, providing a count commensurate with the number of harmful reconvergence structures containing each respective memory element; (d) removing a memory element having the highest count; and (e) repeating steps (a) to (d) with the memory element in step (d) removed.
Claim 2
Independent Claim
88 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) finding reconvergence structures in the: circuit to be tested; (b) determining harmful reconvergence structures containing memory elements; (c) for each respective memory element in a harmful reconvergence structure, providing a count commensurate with the number of harmful reconvergence structures containing each respective memory element; (d) removing a memory element having the highest count; and (e) repeating steps (a) to (d) with the memory element in step (d) removed.
Claim 3
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 1, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (d) are the scan elements.
Claim 4
Dependent Claim
69 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 1, further including steps (f) and (g) after performing step (c), where step (f) is deriving a S-graph of the circuit to be tested and step (g) is identifying strongly connected components in said S-graph, and where step (d) removes a memory element having the highest count from a strongly connected component.
Claim 5
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 3, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (d) are the scan elements.
Claim 6
Dependent Claim
42 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 3, where step (d) is performed on the strongly connected component having the largest size in the S-graph derived from the circuit to be tested.
Claim 7
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 5, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (d) are the scan elements.
Claim 8
Dependent Claim
36 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 5 where step (c) is repeated until all strongly connected components have a size less than a predetermined size.
Claim 9
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 7, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (d) are the scan elements.
Claim 10
Dependent Claim
32 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 1, where step (e) is performed until a predetermined number of memory elements are removed.
Claim 11
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 9, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (d) are the scan elements.
Claim 12
Independent Claim
161 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) for pairs of flip-flops in a reconvergence path (i) performing fanout checks and characterizing pairs of flip-flops as NONE, EQ, INEQ and BOTH and (ii) performing fanin checks and characterizing pairs of flip-flops as NONE, EQ, INEQ, and BOTH; (b) checking for each pair of flip-flops whether any of the following criteria is met: fanout check≠NONE and fanin check≠BOTH or fanin check≠NONE and fanout check≠BOTH or fanout check≠EQ and fanout check≠INEQ or fanout check≠INEQ and fanout check≠EQ; (c) if for any pair of flip-flops at least one criteria is met, for both flip-flops in the pair incrementing a count indicative of a reconvergence and then perform steps (a), (b) and (d) for another pair of flip-flops; (d) if for any pair of flip-flops none of the criteria is met, perform steps (a), (b), (c) and (d) for another pair of flip-flops.
Claim 13
Independent Claim
161 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) for pairs of flip-flops in a reconvergence path (i) performing fanout checks and characterizing pairs of flip-flops as NONE, EQ, INEQ and BOTH and (ii) performing fanin checks and characterizing pairs of flip-flops as NONE, EQ, INEQ, and BOTH; (b) checking for each pair of flip-flops whether any of the following criteria is met: fanout check≠NONE and fanin check≠BOTH or fanin check≠NONE and fanout check≠BOTH or fanout check≠EQ and fanout check≠INEQ or fanout check≠INEQ and fanout check≠EQ; (c) if for any pair of flip-flops at least one criteria is met, for both flip-flops in the pair incrementing a count indicative of a reconvergence and then perform steps (a), (b) and (d) for another pair of flip-flops; (d) if for any pair of flip-flops none of the criteria is met, perform steps (a), (b), (c) and (d) for another pair of flip-flops.
Claim 14
Dependent Claim
69 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 11, further comprising the steps of: (e) deriving a S-graph of the circuit to be tested; (f) identifying strongly connected components in the S-graph; and (g) selecting the largest strongly connected components in the S-graph and remove all reconvergences containing the flip-flop having the highest count in the largest strongly connected components.
Claim 15
Dependent Claim
73 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 12; further comprising the steps of: (h) repeat steps (a), (b), (c) and (d) for each remaining pairs of flip-flops; (i) repeat steps (e), (f) and (g) for the circuit without the flip-flop selected in previous step (g); and (j) repeat steps (h) and (i) until all strongly connected components are less than a predetermined size.
Claim 16
Dependent Claim
49 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 13, further comprising the steps of (1) testing the circuit to be tested by the partial scan method where the flip-flops selected in repeated steps (g) are used as the scan elements.
Claim 17
Dependent Claim
75 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 12, further comprising the steps of: (h) repeat steps (a), (b), (c) and (d) for each remaining pairs of flip-flops; (i) repeat steps (e), (f) and (g) for the circuit without the flip-flop selected in previous step (g); and (k) repeat steps (h) and (i) until a predetermined number of flip-flops have been selected in repeated steps (g).
Claim 18
Dependent Claim
49 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 15, further comprising the steps of (1) testing the circuit to be tested by the partial scan method where the flip-flops selected in repeated steps (g) are used as the scan elements.
Claim 19
Independent Claim
116 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) finding reconvergence structures in the circuit to be tested; (b) determining harmful reconvergence structures containing memory elements; (c) for each respective memory element in a harmful reconvergence structure, providing a count commensurate with the number of harmful reconvergence structures containing each respective memory element; (d) deriving an S-graph of the circuit to be tested; (e) removing a memory element having the highest count according to a method selected from the group consisting of in-degree count, out-degree count, and articulation point selection; and (f) repeating steps (a) to (e) with the memory element in step (e) removed.
Claim 20
Independent Claim
116 words
A method of selecting scan elements in a circuit to be tested having sequential elements comprising the steps of: (a) finding reconvergence structures in the circuit to be tested; (b) determining harmful reconvergence structures containing memory elements; (c) for each respective memory element in a harmful reconvergence structure, providing a count commensurate with the number of harmful reconvergence structures containing each respective memory element; (d) deriving an S-graph of the circuit to be tested; (e) removing a memory element having the highest count according to a method selected from the group consisting of in-degree count, out-degree count, and articulation point selection; and (f) repeating steps (a) to (e) with the memory element in step (e) removed.
Claim 21
Dependent Claim
46 words
A method of selecting scan elements in a circuit to be tested as set forth in claim 17, further comprising the step of testing the circuit to be tested by the partial scan method where the memory elements removed in step (e) are the scan elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |