Abstract In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from the memory cells to external peripheral circuits, a circuit for controlling the data output buffer, comprising a address transition detector for detecting a transition of an address signal to generate an address transition detect signal in a pulse form, a delay controller for generating a delay control signal, the delay control signal having a logic value set by a manufacturer according to whether the semiconductor memory device has a repaired memory cell, and an output enable signal generator for generating an output enable signal at a time point delayed by a time period from the generation of the address transition detect signal from the address transition detector, the time period being determined based on a logic value of the delay control signal from the delay controller, the output enable signal generator outputting the output enable signal to the data output buffer to control an operating point of the data output buffer. According to the present invention, the operating point of the data output buffer is controlled according to whether the semiconductor memory device has the repaired memory cell. Therefore, the semiconductor memory device has an enhanced data read speed.
In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from said memory cells to external peripheral circuits, a circuit for controlling said data output buffer, comprising: address transition detection means for detecting a transition of an address signal to generate an address transition detect signal in a pulse form; delay control means for generating a delay control signal, said delay control signal having a logic value set by a manufacturer according to whether said semiconductor memory device has a repaired memory cell; and output enable signal generation means for generating an output enable signal at a time point delayed by a time period from the generation of the address transition detect signal from said address transition detection means, the time period being determined based on a logic value of the delay control signal from said delay control means, said output enable signal generation means outputting the output enable signal to said data output buffer to control an operating point of said data output buffer.
Claim 2
Dependent Claim
176 words
In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from said memory cells to external peripheral circuits, a circuit for controlling said data output buffer, comprising: address transition detection means for detecting a transition of an address signal to generate an address transition detect signal in a pulse form; delay control means for generating a delay control signal, said delay control signal having a logic value set by a manufacturer according to whether said semiconductor memory device has a repaired memory cell; and output enable signal generation means for generating an output enable signal at a time point delayed by a time period from the generation of the address transition detect signal from said address transition detection means, the time period being determined based on a logic value of the delay control signal from said delay control means, said output enable signal generation means outputting the output enable signal to said data output buffer to control an operating point of said data output buffer.
Claim 3
Dependent Claim
66 words
A data output buffer control circuit as set forth in claim 1, wherein said delay control means includes: a fuse opened or closed by the manufacturer according to whether said semiconductor memory device has the repaired memory cell; and latch means for latching an output signal from said fuse and outputting the latched signal as the delay control signal to said output enable signal generation means.
Claim 4
Dependent Claim
99 words
A data output buffer control circuit as set forth in claim 1, wherein said output enable signal generation means includes: variable delay means for delaying variably the address transition detect signal from said address transition detection means by the time period based on the logic value of the delay control signal from said delay control means; and logic means for combining logically an output signal from said variable delay means with a column address strobe signal, a column decoding signal and a read signal and outputting the resultant signal as the output enable signal to said data output buffer.