Data processor with rename buffer and FIFO buffer for in-order instruction completion

Claim 2

A data processor comprising: first calculation circuitry generating a plurality of pairs of results from a plurality of sets of supplied operands and received programmed instructions, each one of the plurality of pairs of results comprising a first and a second result, the received programmed instructions being a subset of an instruction stream, the first calculation circuitry generating the plurality of pairs of results in an out-of-order sequence with respect to a sequence of the instruction stream; a rename buffer coupled to the first calculation circuitry, the rename buffer storing a series of first results received from the first calculation circuitry, the rename buffer outputting the series of first results to a first predetermined register according to the sequence of the instruction stream; and a queue coupled to the first calculation circuitry, the queue storing the series of second results, the queue outputting the series of second results to a second predetermined register according to the sequence of the instruction stream.

Claim 3

The data processor of claim 1 further comprising circuitry for logically ORing a Nth bit of a predetermined one of the series of second results and a Nth bit of the second predetermined register, where N is an integer index, to generate a cumulative value of the Nth bit of the predetermined register, the cumulative value of the Nth bit representing the occurrence of a predetermined condition in at least one of the series of second results.

Claim 4

The data processor of claim 1 wherein the first results received from the calculation circuitry are represented in floating point notation.

Claim 5

The data processor of claim 1 further comprising: second calculation circuitry coupled to the rename buffer, the second calculation circuitry generating a third result from supplied operands and received programmed instructions; and wherein the rename buffer stores a series of third results received from the second calculation circuitry, the rename buffer outputting the series of third results to the first predetermined register according to the sequence of the instruction stream.

Claim 6

The data processor of claim 1 wherein the queue comprises: a first latching element storing a received second result responsive to a first control signal, the first latching element generating a first output; multiplexer circuit selectively outputting one of a received second result or the first output responsive to a second control signal, the multiplexer circuit generating a second output; a second latching element coupled to the multiplexer circuit, the second latching element storing the second output responsive to a third control signal, the second latching element generating the series of second results; and state machine circuitry generating the first, second and third control signals.

Claim 7

The data processor of claim 1 wherein a number of entries in the rename buffer is not equal to a number of entries in the queue.

Claim 8

A data processor comprising: first calculation circuitry generating a first and a second series of results from supplied operands and received programmed instructions, the received programmed instructions being a subset of an instruction stream, the first calculation circuitry generating the first and second series of results in an out-of-order sequence with respect to the instruction stream; a rename buffer coupled to the first calculation circuitry, the rename buffer storing a series of first results received from the first calculation circuitry, the rename buffer outputting the series of first results to a first predetermined register, according to the sequence of the instruction stream; a queue coupled to the first calculation circuitry, the queue storing the series of second results, the queue outputting the series of second results to a second predetermined register according to the sequence of the instruction stream, the queue buffer comprising: a first latching element storing a received second result responsive to a first control signal, the first latching element generating a first output; a multiplexer circuit selectively outputting one of a received second result or the first output responsive to a second control signal, the multiplexer circuit generating a second output; a second latching element coupled to the multiplexer circuit, the second latching element storing the second output responsive to a third control signal, the second latching element outputting the second series of results to the second predetermined register; and a state machine circuitry generating the first, second and third control signals.

Claim 9

A data processor comprising: first calculation circuitry generating a first and a second series of results from supplied operands and received programmed instructions, the received programmed instructions being a subset of an instruction stream, the first calculation circuitry generating the first and second series of results in an out-of-order sequence with respect to the instruction stream; a rename buffer coupled to the first calculation circuitry, the rename buffer storing a series of first results received from the first calculation circuitry, the rename buffer outputting the series of first results to a first predetermined register, according to the sequence of the instruction stream; a queue coupled to the first calculation circuitry, the queue storing the series of second results, the queue outputting the series of second results to a second predetermined register according to the sequence of the instruction stream, the queue buffer comprising: a first latching element storing a received second result responsive to a first control signal, the first latching element generating a first output; a multiplexer circuit selectively outputting one of a received second result or the first output responsive to a second control signal, the multiplexer circuit generating a second output; a second latching element coupled to the multiplexer circuit, the second latching element storing the second output responsive to a third control signal, the second latching element outputting the second series of results to the second predetermined register; and a state machine circuitry generating the first, second and third control signals.

Claim 10

The data processor of claim 7 further comprising circuitry for logically ORing a Nth bit of a predetermined one of the series of second results and a Nth bit of the second predetermined register, where N is an integer index, to generate a cumulative value of the Nth bit of the predetermined register, the cumulative value of the Nth bit representing the occurrence of a predetermined condition in at least one of the series of second results.

Claim 11

The data processor of claim 8 further comprising: second calculation circuitry coupled to the rename buffer, the second calculation circuitry generating a third result from the supplied operands and the received programmed instructions; and wherein the rename buffer stores a series of third results received from the second calculation circuitry, the rename buffer outputting the series of third results to the first predetermined register.

Claim 12

The data processor of claim 7 further comprising: second calculation circuitry coupled to the rename buffer, the second calculation circuitry generating a third result from the supplied operands and the received programmed instructions; and wherein the rename buffer stores a series of third results received from the second calculation circuitry, the rename buffer outputting the series of third results to the first predetermined register.