Precision duty cycle phase lock loop

Claim 2

A precision demodulator, for providing a demodulated output signal in response to an input signal, comprising: means for receiving an input signal at a predetermined frequency; clock means including a clock for providing clock pulses; a bi-directional counter coupled to said clock means; control means responsive to said input signal for providing a control signal causing said bi-directional counter to count a predetermined number of pulses in a first direction in response to said input signal and an equal number of pulses in a second direction immediately thereafter; and means responsive to said control signal for providing said demodulated output signal at a substantially constant duty cycle independent of changes in the frequency of the input signal.

Claim 3

A precision demodulator as recited in claim 1, further including a phase detector having a first input coupled to said input signal receiving means, a second input coupled to said control means and an output; and a voltage controlled oscillator having an input coupled to the output of said phase detector and an output coupled to said control means.

Claim 4

A precision demodulator as recited in claim 1, further including: means including a preset counter having a predetermined number stored therein; means including a comparator coupled to said bi-directional counter and said preset counter for comparing said predetermined number in the preset counter with a count in the bi-directional counter when the count in the bi-directional counter is changed from said first direction to said second direction; and means for adjusting said predetermined number in the preset counter until it corresponds to the count in the bi-directional counter when the count in the bi-directional counter is changed from said first direction to said second direction.

Claim 5

A precision duty cycle tracking loop for providing an output signal having equal width first and second half cycles, comprising: means for receiving an input signal at a predetermined frequency having full cycles comprised of first and second half cycles; a bi-directional counter; means for controlling said bi-directional counter responsive to said input signal for causing said bi-directional counter to count in a first direction during a full cycle of said input signal and to count an equal number of counts in a second direction immediately thereafter; and means for detecting transitions between counting directions of said bi-directional counter for providing said output signal, wherein said output signal has equal width first and second half cycles independent of the frequency of said input signal.

Claim 6

A precision duty cycle tracking loop for providing an output signal having equal width first and second half cycles, comprising: means for receiving an input signal at a predetermined frequency having full cycles comprised of first and second half cycles; a bi-directional counter; means for controlling said bi-directional counter responsive to said input signal for causing said bi-directional counter to count in a first direction during a full cycle of said input signal and to count an equal number of counts in a second direction immediately thereafter; and means for detecting transitions between counting directions of said bi-directional counter for providing said output signal, wherein said output signal has equal width first and second half cycles independent of the frequency of said input signal.

Claim 7

A precision duty cycle tracking loop as recited in claim 4, wherein said input signal receiving means includes a phase detector and a voltage controlled oscillator.

Claim 8

A precision duty cycle tracking loop for providing an output signal having equal width first and second half cycles, comprising: means for receiving an input signal having full cycles comprising of first and second half cycles said input signal receiving means including a phase detector and a voltage controlled oscillator; a bi-directional counter; means for controlling said bi-directional counter responsive to said input signal for causing said bi-directional counter to count in a first direction during a full cycle of said input signal and to count an equal number of counts in a second direction immediately thereafter; means for detecting transitions between counting directions of said bi-directional counter for providing said output signal; wherein said bi-directional counter provides an underflow signal when the count in the second direction has been completed and wherein said detecting means includes said control means, said control means being responsive to said voltage controlled oscillator and to said underflow signal for providing said output signal, said output signal being coupled to said phase detector for comparison with said input signal.

Claim 9

A precision duty cycle tracking loop for providing an output signal having equal width first and second half cycles, comprising: means for receiving an input signal having full cycles comprising of first and second half cycles said input signal receiving means including a phase detector and a voltage controlled oscillator; a bi-directional counter; means for controlling said bi-directional counter responsive to said input signal for causing said bi-directional counter to count in a first direction during a full cycle of said input signal and to count an equal number of counts in a second direction immediately thereafter; means for detecting transitions between counting directions of said bi-directional counter for providing said output signal; wherein said bi-directional counter provides an underflow signal when the count in the second direction has been completed and wherein said detecting means includes said control means, said control means being responsive to said voltage controlled oscillator and to said underflow signal for providing said output signal, said output signal being coupled to said phase detector for comparison with said input signal.

Claim 10

A phase lock loop comprising: a phase detector having first and second inputs and an output that provides an output signal representative of a difference in phases of signals applied to the first and second inputs; means for applying an input signal to said first input; a voltage controlled oscillator having a frequency control input coupled to said output of said phase detector, said oscillator providing an oscillatory output signal; a clock having an output providing clock pulses; a bi-directional counter having an input coupled to said output of said clock for receiving clock pulses, a control input for selecting whether said bi-directional counter counts in a first direction or a second direction and an underflow output for providing an underflow output signal when said count has reached a predetermined value when counting in said second direction; and control means responsive to said voltage controlled oscillator and to said underflow signal, said control means providing a control signal to said bi-directional counter for changing the direction of said count.

Claim 11

A phase lock loop comprising: a phase detector having first and second inputs and an output that provides an output signal representative of a difference in phases of signals applied to the first and second inputs; means for applying an input signal to said first input; a voltage controlled oscillator having a frequency control input coupled to said output of said phase detector, said oscillator providing an oscillatory output signal; a clock having an output providing clock pulses; a bi-directional counter having an input coupled to said output of said clock for receiving clock pulses, a control input for selecting whether said bi-directional counter counts in a first direction or a second direction and an underflow output for providing an underflow output signal when said count has reached a predetermined value when counting in said second direction; and control means responsive to said voltage controlled oscillator and to said underflow signal, said control means providing a control signal to said bi-directional counter for changing the direction of said count.

Claim 12

A precision demodulator comprising: means for receiving an input signal; a bi-directional counter; a clock; means for applying pulses from said clock to said bi-directional counter under the control of said input signal; a preset counter having a predetermined count stored therein; means including a comparator coupled to said bi-directional counter and to said preset counter for comparing the counts therein and providing an equivalence signal when the counts are equal, said bi-directional counter being responsive to said equivalence signal for reversing the count from a first to a second direction, said bi-directional counter being operative to provide an underflow signal when the count in the second direction is complete, said count in the second direction being complete when the number of said counts in said second direction is the same as the number of said counts in said first direction; and means responsive to said equivalence signal and to said underflow signal for providing an output signal.

Claim 13

A precision demodulator comprising: means for receiving an input signal; a bi-directional counter; a clock; means for applying pulses from said clock to said bi-directional counter under the control of said input signal; a preset counter having a predetermined count stored therein; means including a comparator coupled to said bi-directional counter and to said preset counter for comparing the counts therein and providing an equivalence signal when the counts are equal, said bi-directional counter being responsive to said equivalence signal for reversing the count from a first to a second direction, said bi-directional counter being operative to provide an underflow signal when the count in the second direction is complete, said count in the second direction being complete when the number of said counts in said second direction is the same as the number of said counts in said first direction; and means responsive to said equivalence signal and to said underflow signal for providing an output signal.

Claim 16

A method as recited in claim 9, further including utilizing a phase detector to compare the phases of said input signal and said output signal; controlling an oscillator in response to said phase difference; and providing the control signal in response to signals from said oscillator.

Claim 17

A method as recited in claim 9, further including: pre-setting a preset counter to a predetermined number; comparing said predetermined number in the preset counter with the count in the bi-directional counter when the direction of the count in the bi-directional counter is changed; and adjusting the number in the preset counter until it corresponds to the count in the bi-directional counter when the direction of the count is changed.