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US5498571A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device having reliable multi-layered wiring

Assignee: Toshiba Corp
•
Filing: 1995-06-01
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Granted: 1996-03-12
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Expires: 2015-06-01
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Abstract

Abstract An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO 2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.

Inventors

  • 👤 Kazuya Mori
  • 👤 Kenichi Otsuka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 17:44
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10W20/031; H10W20/063; Y; Y10; Y10S; Y10S438/00; Y10S438/937

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 82 words
A method of manufacturing a semiconductor device, comprising the steps of: depositing a conductive layer above a semiconductor substrate; forming a first carbon layer on the conductive layer; patterning the first carbon layer and the conductive layer, thereby forming a first interconnection layer which comprises the first carbon layer and the conductive layer; forming a second carbon layer on side surfaces of the first interconnection layer; and depositing an interlayer insulating layer on the second carbon layer and the first interconnection layer.
Claim 2
Independent Claim 82 words
A method of manufacturing a semiconductor device, comprising the steps of: depositing a conductive layer above a semiconductor substrate; forming a first carbon layer on the conductive layer; patterning the first carbon layer and the conductive layer, thereby forming a first interconnection layer which comprises the first carbon layer and the conductive layer; forming a second carbon layer on side surfaces of the first interconnection layer; and depositing an interlayer insulating layer on the second carbon layer and the first interconnection layer.
Claim 3
Dependent Claim 21 words
The method according to claim 1, wherein the first and second carbon layers prevent hillocks from growing from the conductive layer.
Claim 4
Dependent Claim 17 words
The method according to claim 1, wherein the interlayer insulating layer is deposited at a high temperature.
Claim 5
Dependent Claim 16 words
The method according to claim 1, wherein the conductive layer is made of an Al alloy.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-03-12 1999-09-11 2000-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-03-12 2003-09-11 2004-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-03-12 2007-09-11 2008-03-12 $7700.00 Window Closed / Lapsed

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