Variable-slope driver for pullup-terminated transmission lines

Claim 2

A transmission line driver circuit, comprising: a first N-type field-effect transistor (N-FET) having a conductive channel including a source connected to ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pull termination to a positive termination voltage supply (Vt) relative to ground; a second N-FET having a source connected to ground and having a gate and drain connected together, said second N-FET having a threshold voltage substantially the same as a threshold voltage of said first N-FET; a third N-FET substantially smaller than said second N-FET and having a source connected to ground, having a drain connected to both the gate and drain of said second N-FET, and having a gate connected to an input node (IN) of said circuit; and a fourth N-FET having a conductive channel connected between the gate of said first N-FET and said drain of said second N-FET and having a gate connected to said input node (IN) such that during a logical LOW to HIGH transition at the input node (IN), a transition slope from logical LOW to HIGH at the output node (OUT) is steep until the threshold voltage of the first N-FET is reached and thereafter is less steep, as determined by a ratio of size between the third N-FET and the second N-FET.

Claim 3

A circuit according to claim 1, wherein said third N-FET is approximately 7 times smaller than said second N-FET.

Claim 4

A circuit according to claim 1, wherein said fourth N-FET is substantially the same size as said second N-FET.

Claim 5

A transmission line driver circuit, comprising: a first N-Type filed-effect transistor (N-FET) having its conductive channel including a source connected ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pullup termination to a positive termination supply (Vt) relative to ground; a first P-type field-effect transistor (P-FET) having a source connected to a positive supply node (VDD), having a drain and having a gate coupled to said output node (OUT) through a buffer having a buffer voltage threshold; a second P-FET substantially smaller than said first P-FET and having a source connected to said node (VDD), having a drain connected to said drain of said first P-FET, and having a gate connected to an input node (IN) of said circuit; and a third P-FET having its conductive channel connected between the gate of said first N-FET and said drain of said first P-FET and having its gate connected to said input node (IN), such that during a logical HIGH to LOW transition at the input node (IN), a transition slope from logical HIGH to LOW at the output node (OUT) is less steep as determined by a ratio of size between the smaller second P-FET and the first P-FET until the buffer voltage threshold is reached whereupon the first P-FET conducts and increases a slope of a control voltage at the grate of the first N-FET causing a more steep transition slope from logical HIGH to LOW at the output node (OUT).

Claim 6

A transmission line driver circuit, comprising: a first N-Type filed-effect transistor (N-FET) having its conductive channel including a source connected ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pullup termination to a positive termination supply (Vt) relative to ground; a first P-type field-effect transistor (P-FET) having a source connected to a positive supply node (VDD), having a drain and having a gate coupled to said output node (OUT) through a buffer having a buffer voltage threshold; a second P-FET substantially smaller than said first P-FET and having a source connected to said node (VDD), having a drain connected to said drain of said first P-FET, and having a gate connected to an input node (IN) of said circuit; and a third P-FET having its conductive channel connected between the gate of said first N-FET and said drain of said first P-FET and having its gate connected to said input node (IN), such that during a logical HIGH to LOW transition at the input node (IN), a transition slope from logical HIGH to LOW at the output node (OUT) is less steep as determined by a ratio of size between the smaller second P-FET and the first P-FET until the buffer voltage threshold is reached whereupon the first P-FET conducts and increases a slope of a control voltage at the grate of the first N-FET causing a more steep transition slope from logical HIGH to LOW at the output node (OUT).

Claim 7

A circuit according to claim 4, wherein said second P-FET is approximately 3.5 times smaller than said first P-FET.

Claim 8

A circuit according to claim 4, wherein said third P-FET is substantially the same size as said first P-FET.

Claim 9

A transmission line driver circuit, comprising: a first N-type field-effect transistor (N-FET) having a conductive channel including a source connected to ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pullup termination to a positive termination voltage supply (Vt) relative to ground; a second N-FET having a source connected to ground and having a gate and drain connected together, said second N-FET having a threshold voltage substantially the same as a threshold voltage of said first N-FET; a third N-FET substantially smaller than said second N-FET and having a source connected to ground, having a drain connected to both the gate and drain of said second N-FET, and having a gate connected to an input node (IN) of said circuit; a fourth N-FET substantially the same size as said second N-FET and having a conductive channel connected between the gate of said first N-FET and said drain of said second N-FET and having a gate connected to said input node (IN), a first P-type field-effect transistor (P-FET) having a source connected to a positive supply node (VDD), having a drain and having a gate coupled to said output node (OUT) through a buffer having a buffer voltage threshold; a second P-FET substantially smaller than said first P-FET and having a source connected to said (VDD), having a drain connected to said drain of said first P-FET, and having a gate connected to an input node (IN) of said circuit; and a third P-FET having its conductive channel connected between the gate of said first N-FET and said drain of said first P-FET and having its gate connected to said input node (IN), such that during a logical LOW to HIGH transistion at the input node (IN), a transition slope from logical LOW to HIGH at the output node (OUT) is steep until the threshold voltage of the first N-FET is reached and thereafter is less steep, as determined by a ratio of size between the smaller third N-FET and the second N-FET; and, such that during a logical HIGH to LOW transition at the input node (IN), a transition slope from logical HIGH to LOW at the output node (OUT) is less steep as determined by a ratio of size between the smaller second P-FET and the first P-FET until the buffer voltage threshold is reached whereupon the first P-FET conducts and increases a slope of a control voltage at the gate of the first N-FET causing a more steep transition slope from logical HIGH to LOW at the output node (OUT).

Claim 10

A transmission line driver circuit, comprising: a first N-type field-effect transistor (N-FET) having a conductive channel including a source connected to ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pullup termination to a positive termination voltage supply (Vt) relative to ground; a second N-FET having a source connected to ground and having a gate and drain connected together, said second N-FET having a threshold voltage substantially the same as a threshold voltage of said first N-FET; a third N-FET substantially smaller than said second N-FET and having a source connected to ground, having a drain connected to both the gate and drain of said second N-FET, and having a gate connected to an input node (IN) of said circuit; a fourth N-FET substantially the same size as said second N-FET and having a conductive channel connected between the gate of said first N-FET and said drain of said second N-FET and having a gate connected to said input node (IN), a first P-type field-effect transistor (P-FET) having a source connected to a positive supply node (VDD), having a drain and having a gate coupled to said output node (OUT) through a buffer having a buffer voltage threshold; a second P-FET substantially smaller than said first P-FET and having a source connected to said (VDD), having a drain connected to said drain of said first P-FET, and having a gate connected to an input node (IN) of said circuit; and a third P-FET having its conductive channel connected between the gate of said first N-FET and said drain of said first P-FET and having its gate connected to said input node (IN), such that during a logical LOW to HIGH transistion at the input node (IN), a transition slope from logical LOW to HIGH at the output node (OUT) is steep until the threshold voltage of the first N-FET is reached and thereafter is less steep, as determined by a ratio of size between the smaller third N-FET and the second N-FET; and, such that during a logical HIGH to LOW transition at the input node (IN), a transition slope from logical HIGH to LOW at the output node (OUT) is less steep as determined by a ratio of size between the smaller second P-FET and the first P-FET until the buffer voltage threshold is reached whereupon the first P-FET conducts and increases a slope of a control voltage at the gate of the first N-FET causing a more steep transition slope from logical HIGH to LOW at the output node (OUT).

Claim 11

A transmission line driver circuit for driving an output signal onto a transmission line connected through a termination resistance to a termination positive voltage supply (Vt) comprising: a first n-channel field-effect transistor (N-FET) (Q2) having its conductive channel connected between ground and an output node (OUT) of said circuit which is connected to said transmission line and having its gate connected to a circuit node (A); a second N-FET (Q7) having its conductive channel connected between said output node (OUT) and a positive supply node (VDD) and having its gate connected to a circuit node (B); a third N-FET (Q12) having a drain connected to said node (A) and having its gate connected to an input node (IN) of said circuit; a fourth N-FET (Q11) having its gate and drain connected to the source of said third N-FET (Q12) and having a source connected to ground, said fourth N-FET (Q11) being substantially the same size as said third N-FET (Q12) and having a threshold voltage substantially the same as that of said first N-FET (Q2); a fifth N-FET (Q10) having its conductive channel connected between said source of said third N-FET (Q12) and ground and having its gate connected to said input node (IN), said fifth N-FET (Q10) being substantially smaller than said third and fourth N-FETs (Q11 and Q12); a first P-type field-effect transistor (P-FET) (Q13) having a source connected to said node (A) and having its gate connected to said input node (IN); a second P-FET (Q15) having its conductive channel connected between a drain of said first P-FET (Q13) and said node (VDD), said second P-FET (Q15) being substantially the same size as said first P-FET (Q13); a third P-FET (Q14) having its conductive channel connected between said drain of said first P-FET (Q13) and said node (VDD) and having its gate connected to said input node (IN), said third P-FET (Q14) being substantially smaller than said first and second P-FETs (Q13 and Q15); a first buffer (24) having an input connected to said output node (OUT) and having an output connected to the gate of said second P-FET (Q15); an inverting logic gate (22) having a first input and having an output connected to said node (B); a second buffer (20) having an input connected to said node (A) and an output connected to said first input of said inverting logic gate (22); a sixth N-FET (Q18) having a drain connected to said node B and having its gate connected to said output node (OUT); a seventh N-FET (Q17) having a drain connected to said node (VDD), having a source connected to the source of said sixth N-FET (Q18), and having a gate connected to a reference voltage node (REF) to which a reference-voltage-generating circuit is connected; and an eighth N-FET (Q16) having its conductive channel connected between said source of said sixth N-FET (Q18) and ground and having its gate connected to said node (VDD).

Claim 12

A transmission line driver circuit for driving an output signal onto a transmission line connected through a termination resistance to a termination positive voltage supply (Vt) comprising: a first n-channel field-effect transistor (N-FET) (Q2) having its conductive channel connected between ground and an output node (OUT) of said circuit which is connected to said transmission line and having its gate connected to a circuit node (A); a second N-FET (Q7) having its conductive channel connected between said output node (OUT) and a positive supply node (VDD) and having its gate connected to a circuit node (B); a third N-FET (Q12) having a drain connected to said node (A) and having its gate connected to an input node (IN) of said circuit; a fourth N-FET (Q11) having its gate and drain connected to the source of said third N-FET (Q12) and having a source connected to ground, said fourth N-FET (Q11) being substantially the same size as said third N-FET (Q12) and having a threshold voltage substantially the same as that of said first N-FET (Q2); a fifth N-FET (Q10) having its conductive channel connected between said source of said third N-FET (Q12) and ground and having its gate connected to said input node (IN), said fifth N-FET (Q10) being substantially smaller than said third and fourth N-FETs (Q11 and Q12); a first P-type field-effect transistor (P-FET) (Q13) having a source connected to said node (A) and having its gate connected to said input node (IN); a second P-FET (Q15) having its conductive channel connected between a drain of said first P-FET (Q13) and said node (VDD), said second P-FET (Q15) being substantially the same size as said first P-FET (Q13); a third P-FET (Q14) having its conductive channel connected between said drain of said first P-FET (Q13) and said node (VDD) and having its gate connected to said input node (IN), said third P-FET (Q14) being substantially smaller than said first and second P-FETs (Q13 and Q15); a first buffer (24) having an input connected to said output node (OUT) and having an output connected to the gate of said second P-FET (Q15); an inverting logic gate (22) having a first input and having an output connected to said node (B); a second buffer (20) having an input connected to said node (A) and an output connected to said first input of said inverting logic gate (22); a sixth N-FET (Q18) having a drain connected to said node B and having its gate connected to said output node (OUT); a seventh N-FET (Q17) having a drain connected to said node (VDD), having a source connected to the source of said sixth N-FET (Q18), and having a gate connected to a reference voltage node (REF) to which a reference-voltage-generating circuit is connected; and an eighth N-FET (Q16) having its conductive channel connected between said source of said sixth N-FET (Q18) and ground and having its gate connected to said node (VDD).

Claim 13

A circuit according to claim 1 further comprising: a pullup transistor connected between said output node (OUT) and a positive supply node (VDD), said pullup transistor being a fifth N-FET; reference voltage providing means for providing a reference voltage within a range between said termination voltage and a predetermined minimum voltage representing a logical HIGH at said output node (OUT); and a differential amplifier having one input coupled to said reference voltage providing means and having another input coupled said output node (OUT) and having an output connected to a control gate of said pullup transistor, said differential amplifier for substantially turning off said pullup transistor when a feedback signal from said output node (OUT) exceeds said reference voltage.

Claim 14

A circuit according to claim 9, further comprising a logic gate having a first input connected to the gate of the first N-FET, a second input connected to an enable signal, and an output connected to said pullup transistor and upon which appears a logic signal of said predetermined minimum voltage to operate said pullup transistor when said enable signal is enabled and when said input node (IN) switches to a logical HIGH, and wherein said differential amplifier is coupled to the output of said logic gate and overdrives said logic signal toward to limit the voltage at the output node (OUT) to not exceed the termination voltage (VT) as the voltage on said transmission line approaches said reference voltage.

Claim 15

A circuit according to claim 9 wherein said differential amplifier comprises: a sixth N-FET having a drain connected to a positive supply node (VDD) and a gate connected to said reference voltage providing means; a seventh N-FET having a drain connected to a gate of said pullup transistor, a source connected to a source of said sixth N-FET, and a gate connected to said output node (OUT); and a constant current source having a current output connected to said source of said sixth N-FET.

Claim 16

A circuit according to claim 11, wherein said constant current source comprises an N-FET having its conductive channel connected between said source of said sixth N-FET and ground and having its gate coupled to said node (VDD).

Claim 17

A circuit according to claim 9, wherein said reference voltage generating means comprises a resistive voltage divider network connected between a positive supply node (VDD) and ground.

Claim 18

A circuit according to claim 10, wherein said logic gate is a NOR gate.

Claim 19

A circuit according to claim 8, wherein said inverting logic gate is a two-input NOR gate having a second input connected to an enable node (EN*) of said circuit.