US5105102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer circuit
Assignee: NEC Corp
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Filing: 1991-02-28
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Granted: 1992-04-14
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Expires: 2011-02-28
Abstract
Abstract An output buffer circuit which supplies at an emitter coupled logic (ECL) level logic signals from a logic circuit in an integrated circuit realized by a CMOS process. The logic signals are supplied to the gate electrodes of a first P-channel CMOS transistor and a first N-channel CMOS transistor connected in series. A second P-channel CMOS transistor for amplifying the output signal has an open drain configuration. Between the output terminal of the output from the P-channel CMOS transistor of open drain configuration and an external power supply terminal is connected a first resistor. Voltage regulating means, connected between the output terminal and the external power supply terminal, regulates the output voltage at the output terminal. In the voltage regulating means, a voltage setting circuit produces a desired voltage from a voltage supplied from the external power supply terminal. A control voltage generating circuit so generates a control voltage as to have the voltage at the output terminal regulated by the desired voltage on the basis of the voltage produced by the voltage setting circuit. A regulating driver circuit regulates the voltage at the output terminal to a prescribed voltage with the control voltage.
Inventors
- 👤 Fumio Shioda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:10
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F1/00; G05F1/10; G05F1/46; G05F1/56; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
101 words
An output buffer circuit comprising: output means provided with first amplifying means having a serially connected first P-channel CMOS transistor to whose gate electrode are supplied logic signals and a first N-channel CMOS transistor; second amplifying means, having a second P-channel CMOS transistor of open drain configuration, for amplifying the output signal of said first amplifying means; and a first resistor connected between the output terminal of said second amplifying means and an external power supply terminal; and voltage adjusting means, connected to said output terminal and said external power supply terminal, for adjusting the output voltage of said output terminal.
Claim 2
Dependent Claim
101 words
An output buffer circuit comprising: output means provided with first amplifying means having a serially connected first P-channel CMOS transistor to whose gate electrode are supplied logic signals and a first N-channel CMOS transistor; second amplifying means, having a second P-channel CMOS transistor of open drain configuration, for amplifying the output signal of said first amplifying means; and a first resistor connected between the output terminal of said second amplifying means and an external power supply terminal; and voltage adjusting means, connected to said output terminal and said external power supply terminal, for adjusting the output voltage of said output terminal.
Claim 3
Dependent Claim
91 words
An output buffer circuit, as claimed in claim 1, wherein said voltage adjusting means comprises: a voltage setting circuit for producing a desired voltage from the voltage supplied to said external power supply terminal, a control voltage generating circuit for so generating a control voltage that the voltage of said output voltage be regulated by a prescribed voltage on the basis of the voltage produced by said voltage setting circuit, and a regulating driver circuit for regulating the voltage of said output terminal to the prescribed voltage with said control voltage.
Claim 4
Dependent Claim
46 words
An output buffer circuit, as claimed in claim 2, wherein said voltage setting circuit has a plurality of serially connected resistors connected between said external power supply terminal and a ground potential, and obtains said desired voltage from the connecting point of said serially connected resistors.
Claim 5
Dependent Claim
79 words
An output buffer circuit, as claimed in claim 2, wherein said voltage setting circuit has: a differential amplified whose positive input terminal is connected to said external power supply terminal and whose negative input terminal is supplied with a feedback signal from the output end, and a plurality of serially connected resistors connected between the output end of said differential amplifier and a ground potential, and obtains said desired voltage from the connecting point of said serially connected resistors.
Claim 6
Dependent Claim
81 words
An output buffer circuit, as claimed in claim 2, wherein said control voltage generating circuit has: a differential amplifier whose input terminal is supplied with said desired voltage from said voltage setting circuit, a third P-channel CMOS transistor whose gate electrode is supplied with the output signal of said differential amplifier and whose drain electrode is connected to the positive input terminal of said differential amplifier, wherein: the output signal of said differential amplifier is supplied to said regulating driver circuit.
Claim 7
Dependent Claim
20 words
An output buffer circuit, as claimed in claim 5, wherein said first and second resistors have the same resistance values.
Claim 8
Dependent Claim
39 words
An output buffer circuit, as claimed in claim 2, wherein said regulating driver circuit has a third P-channel CMOS transistor whose gate electrode is supplied with said control voltage and whose drain electrode is connected to said output terminal.
Claim 9
Dependent Claim
149 words
An output buffer circuit, as claimed in claim 2, wherein: said voltage setting circuit has a plurality of serially connected resistors connected between said external power supply terminal and the ground potential, and obtains said desired voltage from the connecting point of said serially connected resistors; said control voltage generating circuit has a differential amplifier whose negative input terminal is supplied with said desired voltage from said voltage setting circuit, and a third P-channel CMOS transistor whose gate electrode is supplied with the output signal of said differential amplifier and whose drain electrode is connected to the positive input terminal of said differential amplifier, wherein the output signal of said differential amplifier is supplied to said regulating driver circuit; and said regulating driver circuit has a fourth P-channel CMOS transistor whose gate electrode is supplied with said control voltage and whose drain electrode is connected to said output terminal.
Claim 10
Dependent Claim
181 words
An output buffer circuit, as claimed in claim 2, wherein: said voltage setting circuit has a differential amplifier whose positive input terminal is connected to said external power supply terminal and whose negative input terminal is supplied with a feedback signal from the output end and a plurality of serially connected resistors connected between the output of said differential amplifier and the ground potential, and obtains said desired voltage from the connecting point of said serially connected resistors; said control voltage generating circuit has a differential amplifier whose negative input terminal is supplied with said desired voltage from said voltage setting circuit, and a third P-channel CMOS transistor whose gate electrode is supplied with the output signal of said differential amplifier and whose drain electrode is connected to the positive input terminal of said differential amplifier, wherein the output signal of said differential amplifier is supplied to said regulating driver circuit; and said regulating driver circuit has a fourth P-channel CMOS transistor whose gate electrode is supplied with said control voltage and whose drain electrode is connected to said output terminal.
Claim 11
Dependent Claim
22 words
An output buffer circuit, as claimed in claim 9, wherein said third and fourth P-channel CMOS transistors have the same performance characteristics.
Claim 12
Dependent Claim
56 words
An output buffer circuit, as claimed in claim 2, wherein: said output means has a second N-channel CMOS transistor whose gate electrode is supplied with a bias voltage, and said voltage regulating circuit has bias voltage generating means for generating said bias voltage on the basis of the voltage supplied from said external power supply terminal.
Claim 13
Dependent Claim
107 words
An output buffer circuit, as claimed in claim 11, wherein: said voltage setting circuit generates a second desired voltage different from said desired voltage, and said bias voltage generating means has a serial circuit including said fifth P-channel CMOS transistor and third N-channel CMOS transistor connected in series, a sixth P-channel CMOS transistor connected to said serial circuit, and a differential amplifier whose positive input terminal is supplied with said second desired voltage and to whose negative input terminal is connected the drain electrode of said sixth P-channel CMOS transistor, wherein the output of said differential amplifier is supplied to said output means as said bias voltage.
Claim 14
Dependent Claim
26 words
An output buffer circuit, as claimed in claim 12, wherein said serial circuit has a third N-channel CMOS transistor whose gate electrode receives said bias voltage.
Claim 15
Dependent Claim
42 words
An output buffer circuit, as claimed in claim 1, wherein a plurality of said output buffer circuits are provided and the output voltage of said output terminal of each of said plural output buffer circuit is regulated by said voltage regulating circuit.
References Cited (Backward Citations)
US5043604A
Cited
US5043607A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-14 | 1995-10-14 | 1996-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-14 | 1999-10-14 | 2000-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-14 | 2003-10-14 | 2004-04-14 | $7700.00 | Window Closed / Lapsed |