Patent US5496751A successfully refreshed from Google Patents.
US5496751A
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US
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Method of forming an ESD and hot carrier resistant integrated circuit structure
Assignee: Philips Semiconductors Inc
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Filing: 1995-02-24
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Granted: 1996-03-05
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Expires: 2015-02-24
Abstract
Abstract An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.
Inventors
- 👤 Yi-Hen Wei
- 👤 Ying T. Loh
- 👤 Chung S. Wang
- 👤 Chenming Hu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10P; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
333 words
A method for making an integrated circuit device comprising: providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface; forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side; forming a pair of LDD regions of a second polarity type in said substrate by ion implantation into said substrate at an angle between about 20° C. and 60° C. with respect to said substrate surface, where a drain side LDD region is adjacent to said drain side of said channel to provide hot carrier protection, and where a source side LDD region is adjacent to said source side of said channel; forming dielectric spacers over said substrate surface on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions; forming a drain region in said substrate of said second polarity type at a higher doping level than that of said drain side LDD proximate said drain side LDD region and forming a source region of said second polarity type at a higher doping level than that of the source side LDD in said substrate proximate said source side LDD region by ion implantation into said substrate at an angle between about 80° C. and 90° C. with respect to said substrate surface after the formation of said spacers; forming a drain side DDD region in said substrate after the formation of said dielectric spacers by ion implantation into said substrate at an angle between about 80° C. and 90° C. with respect to said substrate surface; and annealing the substrate to cause migration of the implanted ions such that said drain side DDD region and source side DDD region substantially enclose said respective drain and source regions, said DDD regions acting further to separate said drain and source regions from said respective drain and source side LDD regions.
Claim 2
Independent Claim
333 words
A method for making an integrated circuit device comprising: providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface; forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side; forming a pair of LDD regions of a second polarity type in said substrate by ion implantation into said substrate at an angle between about 20° C. and 60° C. with respect to said substrate surface, where a drain side LDD region is adjacent to said drain side of said channel to provide hot carrier protection, and where a source side LDD region is adjacent to said source side of said channel; forming dielectric spacers over said substrate surface on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions; forming a drain region in said substrate of said second polarity type at a higher doping level than that of said drain side LDD proximate said drain side LDD region and forming a source region of said second polarity type at a higher doping level than that of the source side LDD in said substrate proximate said source side LDD region by ion implantation into said substrate at an angle between about 80° C. and 90° C. with respect to said substrate surface after the formation of said spacers; forming a drain side DDD region in said substrate after the formation of said dielectric spacers by ion implantation into said substrate at an angle between about 80° C. and 90° C. with respect to said substrate surface; and annealing the substrate to cause migration of the implanted ions such that said drain side DDD region and source side DDD region substantially enclose said respective drain and source regions, said DDD regions acting further to separate said drain and source regions from said respective drain and source side LDD regions.
Claim 3
Dependent Claim
55 words
A method for making an integrated circuit device as recited in claim 1 wherein said drain side DDD region further substantially isolates said drain region from a bulk portion of said substrate, and wherein said source side DDD region further isolates said source region from a bulk portion of said substrate to provide ESD protection.
Claim 4
Dependent Claim
27 words
A method for making an integrated circuit device as recited in claim 2 wherein said first polarity type is P, and-wherein said second polarity type is N.
Claim 5
Dependent Claim
44 words
A method for making an integrated circuit device as recited in claim 3, wherein a doping species for the first polarity type includes boron, and wherein a doping species for the second polarity type is selected from the group consisting of phosphorous and arsenic.
Claim 6
Dependent Claim
67 words
A method for making an integrated circuit device as recited in claim 4 wherein said LDD regions are doped at about 1×10 12 to 1×10 14 atoms per cubic centimeter, said source region and said drain region are doped at about 1×10 15 to 1×10 16 atoms per cubic centimeter, and said DDD regions are doped to about 1×10 14 to 5×10 15 atoms per cubic centimeter.
Claim 7
Dependent Claim
24 words
A method for making an integrated circuit device as recited in claim 5 wherein said channel is less than about 1.0 microns in length.
Claim 8
Independent Claim
351 words
A method for making an integrated circuit device having hot carrier and ESD protection comprising the steps of: providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface; forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side; doping said substrate with a second polarity type by ion implantation into said substrate at an angle between 20° C. and 60° C. with respect to said substrate surface, to form a pair of LDD regions in the substrate, where a drain side LDD is adjacent to said drain side of said channel, and where a source side LDD region is adjacent to said source side of said channel; forming dielectric spacers over said substrate on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions and prior to formation of a source side DDD region and a drain side DDD region; doping said substrate with said second polarity type after the formation of said dielectric spacers by ion implantation into said substrate at an angle between 80° C. and 90° C. with respect to said substrate surface, to form a drain region in said substrate proximate said drain side LDD region and to form a source region in said substrate proximate said source side LDD region; and doping said substrate with said second polarity type by ion implantation into said substrate at an angle between 80° C. and 90° C. with respect to said substrate surface and subsequently annealing the substrate to cause migration of the implanted ions to form said drain side DDD region in said substrate which separates said drain region from said drain side LDD region and isolates said drain region from a bulk portion of said substrate, and said source side DDD region in said substrate which separates said source region from said source side LDD region and isolates said source region from a bulk portion of said substrate to provide ESD protection.
Claim 9
Independent Claim
351 words
A method for making an integrated circuit device having hot carrier and ESD protection comprising the steps of: providing a semiconductor substrate of a first polarity type and having a substantially planar substrate surface; forming a gate over said substrate surface, thereby defining a channel in said substrate having a source side and a drain side; doping said substrate with a second polarity type by ion implantation into said substrate at an angle between 20° C. and 60° C. with respect to said substrate surface, to form a pair of LDD regions in the substrate, where a drain side LDD is adjacent to said drain side of said channel, and where a source side LDD region is adjacent to said source side of said channel; forming dielectric spacers over said substrate on said drain side of said gate sidewall and on said source side of said gate sidewall after formation of said source and said drain side LDD regions and prior to formation of a source side DDD region and a drain side DDD region; doping said substrate with said second polarity type after the formation of said dielectric spacers by ion implantation into said substrate at an angle between 80° C. and 90° C. with respect to said substrate surface, to form a drain region in said substrate proximate said drain side LDD region and to form a source region in said substrate proximate said source side LDD region; and doping said substrate with said second polarity type by ion implantation into said substrate at an angle between 80° C. and 90° C. with respect to said substrate surface and subsequently annealing the substrate to cause migration of the implanted ions to form said drain side DDD region in said substrate which separates said drain region from said drain side LDD region and isolates said drain region from a bulk portion of said substrate, and said source side DDD region in said substrate which separates said source region from said source side LDD region and isolates said source region from a bulk portion of said substrate to provide ESD protection.
Claim 10
Dependent Claim
47 words
A method for making an integrated circuit device as recited in claim 7 wherein said spacers are formed by first depositing a SiO 2 layer to a thickness of between about 1000 and 5000 angstroms, and then anisotropically etching said SiO 2 layer to form said spacers.
Claim 11
Dependent Claim
45 words
A method for making an integrated circuit device as recited in claim 8 wherein said step of depositing a SiO 2 layer is accomplished with a TEOS process, and wherein said step of anisotropically etching said SiO 2 layer is accomplished with an RIE process.
Claim 12
Dependent Claim
38 words
A method for making an integrated circuit device as recited in claim 7 wherein said step of annealing said substrate to cause migration further causes activation of said drain side DDD region and said source side DDD region.
Claim 13
Dependent Claim
41 words
A method for making an integrated circuit device as recited in claim 10 wherein said LATID type implant is at a density of between about 1×10 12 -1×10 14 atoms/cm 3 , and at an energy of between about 40-90 keV.
Claim 14
Dependent Claim
53 words
A method for making an integrated circuit device as recited in claim 10 wherein said step of doping said substrate to form a drain region and a source region comprises implanting at a density of between about 10 15 -10 16 atoms/cm 3 , and at an energy of between about 40-80 KeV.
Claim 15
Dependent Claim
62 words
A method for making an integrated circuit device as recited in claim 10 wherein said step of doping said substrate to form said drain side DDD region and said source side DDD region comprises the step of implanting said substrate at a density of between about 1×10 14 -5×10 15 atoms/cm 3 , and at an energy of between about 50-100 keV.
Claim 16
Dependent Claim
34 words
A method for making an integrated circuit device as recited in claim 13 wherein said step of annealing said substrate comprises heating said substrate to about 800°-1000° C. for about 0.25 to 2 hours.
Claim 17
Dependent Claim
27 words
A method for making an integrated circuit device as recited in claim 10 wherein said first polarity type is P and said second polarity type is N.
Claim 18
Dependent Claim
36 words
A method for making an integrated circuit device as recited in claim 15 wherein said first polarity type is boron, and wherein said second polarity type is chosen from the group consisting of arsenic and phosphorous.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |