Semiconductor memory device having SOI structure and manufacturing method thereof

Claim 2

A semiconductor memory device having an SOI structure, comprising: a dielectric layer having opposing first and second surfaces; a semiconductor layer formed on said first surface of said dielectric layer; a conductive layer formed on said second surface of said dielectric layer; first and second impurity regions formed to define a channel region in said semiconductor layer; and a gate electrode formed on said channel region with an insulating layer interposed therebetween, wherein a capacitor is formed by said first impurity region, said dielectric layer opposing said first impurity region, and said conductive layer, wherein said conductive layer is a semiconductor substrate, and wherein said semiconductor substrate is made of single crystalline silicon, a first conductivity type impurity having a first concentration is introduced into said semiconductor substrate, and a third impurity region including the first conductivity type impurity having a second concentration higher than said first concentration is formed in a region located directly under said first impurity region in the surface of said semiconductor substrate contacting said dielectric layer.

Claim 3

A semiconductor memory device having an SOI structure, comprising: a dielectric layer having opposing first and second surfaces; a semiconductor layer formed on said first surface of said dielectric layer; a conductive layer formed on said second surface of said dielectric layer; first and second impurity regions formed to define a channel region in said semiconductor layer; and a gate electrode formed on said channel region with an insulating layer interposed therebetween, wherein a capacitor is formed by said first impurity region, said dielectric layer opposing said first impurity region, and said conductive layer, wherein said dielectric layer includes a first dielectric portion having a first relative dielectric constant and a second dielectric portion having a second relative dielectric constant smaller than said first relative dielectric constant, and said first impurity region is located on said first dielectric portion, and said second impurity region is located on said second dielectric portion.

Claim 4

A semiconductor memory device having an SOI structure, comprising: a dielectric layer having opposing first and second surfaces; a semiconductor layer formed on said first surface of said dielectric layer; a conductive layer formed on said second surface of said dielectric layer; first and second impurity regions formed to define a channel region in said semiconductor layer; and a gate electrode formed on said channel region with an insulating layer interposed therebetween, wherein a capacitor is formed by said first impurity region, said dielectric layer opposing said first impurity region, and said conductive layer, wherein said dielectric layer includes a first dielectric portion having a first relative dielectric constant and a second dielectric portion having a second relative dielectric constant smaller than said first relative dielectric constant, and said first impurity region is located on said first dielectric portion, and said second impurity region is located on said second dielectric portion.

Claim 5

The semiconductor memory device according to claim 2, further comprising: an interlayer insulating layer having a contact hole on said second impurity region and covering said semiconductor layer and said gate electrode; and a bit line formed on said interlayer insulating layer and in said contact hole and electrically connected to said second impurity region.

Claim 6

The semiconductor memory device having an SOI structure, including a memory cell array portion where a memory cell is formed and a peripheral circuit portion where a peripheral circuit is formed, comprising: a dielectric layer having opposing first and second surfaces and extending from within said memory cell array portion into said peripheral circuit portion; a semiconductor layer formed on said first surface of said dielectric layer so as to extend from within said memory cell array portion into said peripheral circuit portion; a pair of first impurity regions formed spaced apart from each other in said semiconductor layer located within said memory cell array portion so as to define a first channel region; a first gate electrode formed on said first channel region with a first insulating layer interposed therebetween; a pair of second impurity regions formed spaced apart from each other in said semiconductor layer located within said peripheral circuit portion so as to define a second channel region; a second gate electrode formed on said second channel region with a second insulating layer interposed therebetween; and a conductive layer formed on said second surface of said dielectric layer, wherein said dielectric layer is formed by a first dielectric portion having a first relative dielectric constant within said memory cell array portion, and formed by a second dielectric portion having a second relative dielectric constant smaller than said first relative dielectric constant within said peripheral circuit portion.

Claim 7

The semiconductor memory device having an SOI structure, including a memory cell array portion where a memory cell is formed and a peripheral circuit portion where a peripheral circuit is formed, comprising: a dielectric layer having opposing first and second surfaces and extending from within said memory cell array portion into said peripheral circuit portion; a semiconductor layer formed on said first surface of said dielectric layer so as to extend from within said memory cell array portion into said peripheral circuit portion; a pair of first impurity regions formed spaced apart from each other in said semiconductor layer located within said memory cell array portion so as to define a first channel region; a first gate electrode formed on said first channel region with a first insulating layer interposed therebetween; a pair of second impurity regions formed spaced apart from each other in said semiconductor layer located within said peripheral circuit portion so as to define a second channel region; a second gate electrode formed on said second channel region with a second insulating layer interposed therebetween; and a conductive layer formed on said second surface of said dielectric layer, wherein said dielectric layer is formed by a first dielectric portion having a first relative dielectric constant within said memory cell array portion, and formed by a second dielectric portion having a second relative dielectric constant smaller than said first relative dielectric constant within said peripheral circuit portion.

Claim 8

A semiconductor memory device having an SOI structure, comprising: a first dielectric layer having opposing first and second surfaces; a semiconductor layer formed on said first surface of said dielectric layer; a first conductive layer formed on said second surface of said dielectric layer; first and second impurity regions formed in said semiconductor layer so as to define a channel region; a gate electrode formed on said channel region with an insulating layer interposed therebetween; a second dielectric layer formed on the surface of said first impurity region; and a second conductive layer formed on said second dielectric layer, wherein a first capacitor is formed by said first impurity region said first dielectric layer opposing said first impurity region, and said first conductive layer, and a second capacitor is formed by said first impurity region, said second dielectric layer opposing said first impurity region, and said second conductive layer.

Claim 9

A semiconductor memory device having an SOI structure, comprising: a first dielectric layer having opposing first and second surfaces; a semiconductor layer formed on said first surface of said dielectric layer; a first conductive layer formed on said second surface of said dielectric layer; first and second impurity regions formed in said semiconductor layer so as to define a channel region; a gate electrode formed on said channel region with an insulating layer interposed therebetween; a second dielectric layer formed on the surface of said first impurity region; and a second conductive layer formed on said second dielectric layer, wherein a first capacitor is formed by said first impurity region said first dielectric layer opposing said first impurity region, and said first conductive layer, and a second capacitor is formed by said first impurity region, said second dielectric layer opposing said first impurity region, and said second conductive layer.

Claim 10

The semiconductor memory device according to claim 5, wherein said second dielectric layer extends onto as far as the side surface of said first impurity region.

Claim 11

A semiconductor memory device having an SOI structure, comprising: a substrate; a first dielectric layer formed on said substrate; a gate electrode formed in said first dielectric layer; a semiconductor layer formed on said first dielectric layer; first and second impurity regions formed in said semiconductor layer with an interval so as to form a channel region at a position opposing said gate electrode; a second dielectric layer formed on said semiconductor layer; and a conductive layer formed on said second dielectric layer, wherein a capacitor is formed by said first impurity region, said second dielectric layer opposing said first impurity region, and said conductive layer.

Claim 12

A semiconductor memory device having an SOI structure, comprising: a substrate; a first dielectric layer formed on said substrate; a gate electrode formed in said first dielectric layer; a semiconductor layer formed on said first dielectric layer; first and second impurity regions formed in said semiconductor layer with an interval so as to form a channel region at a position opposing said gate electrode; a second dielectric layer formed on said semiconductor layer; and a conductive layer formed on said second dielectric layer, wherein a capacitor is formed by said first impurity region, said second dielectric layer opposing said first impurity region, and said conductive layer.