Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells

Claim 1

A CMOS DRAM manufacturing process comprising the following sequence of steps: (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate; (b) forming field isolation regions; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer; (e) patterning N-channel gates from a first portion of said first conductive layer, said first portion overlying said P-type regions, while leaving an unetched second portion of said first conductive layer, said second portion overlying the N-type regions; (f) performing at least one N-channel source/drain implant; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions; (h) etching storage-node contact openings through said insulative mold layer; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer, while leaving other portions of said second conductive layer which line said storage-node contact openings, said other portions becoming individual storage-node capacitor plates for individual memory cells; (k) forming a cell dielectric layer superjacent said second conductive layer; (l) forming a third conductive layer superjacent said cell dielectric layer; (m) patterning P-channel gates having vertical sidewalls from the unetched expanse of said first conductive layer; and (n) depositing a dielectric spacer layer; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates; and (p) performing a blanket P-channel source/drain implant.