Patent US5491787A successfully refreshed from Google Patents.
US5491787A
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Fault tolerant digital computer system having two processors which periodically alternate as master and slave
Assignee: Unisys Corp
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Filing: 1994-08-25
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Granted: 1996-02-13
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Expires: 2014-08-25
Abstract
Abstract In a multiprocessor system, at least one processor is acting as a master processor and another processor is acting as the slave or shadow processor that checks operation of the first processor. Periodically, a controller switches operating mode of a master or main processor to slave or shadow mode, and at the same time switches operation of a slave or shadow processor to main or master processing mode. The first processor is then used as a slave or shadow processor to check operation of the second processor.
Inventors
- 👤 Seyed H. Hashemi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1654; G06F11/1637; G06F11/1641
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
142 words
A method of operating a fault tolerant digital computer system of the type which includes first and second processors with each such processor having a) a standalone master operating mode and b) a slave mode for monitoring the other processor, said method comprising the steps of: running said system in one state for a predetermined time interval where said first processor is in said master mode and said second processor is in said slave mode; running said system in an opposite state for another predetermined time interval where said second processor is in said master mode and said first processor is in said slave mode; and, periodicly switching the operation of said system from said one state to said opposite state, and vice-versa, such that said first and second processors are in said master mode during respective time intervals which are interleaved.
Claim 2
Independent Claim
142 words
A method of operating a fault tolerant digital computer system of the type which includes first and second processors with each such processor having a) a standalone master operating mode and b) a slave mode for monitoring the other processor, said method comprising the steps of: running said system in one state for a predetermined time interval where said first processor is in said master mode and said second processor is in said slave mode; running said system in an opposite state for another predetermined time interval where said second processor is in said master mode and said first processor is in said slave mode; and, periodicly switching the operation of said system from said one state to said opposite state, and vice-versa, such that said first and second processors are in said master mode during respective time intervals which are interleaved.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |