US5491434A
Expired / Lapsed
US
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Circuit and method of differential amplitude detection
Assignee: Motorola Solutions Inc
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Filing: 1994-12-05
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Granted: 1996-02-13
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Expires: 2014-12-05
Abstract
Abstract A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V OUT signal for providing an error free true data output signal VTO.
Inventors
- 👤 David B. Harnishfeger
- 👤 Michael J. Pennell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:05
CPC Classifications
H; H04; H04L; H04L1/00; H03; H03D; H03D1/00; H03D1/02; G; G01; G01R; G01R19/00; G01R19/10
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
171 words
A differential amplitude detection circuit, comprising: a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal; a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal; a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component of said differential input signal; a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component of said differential input signal; and a summing circuit having first and second inputs respectively coupled for receiving said first and second peak signals and having an output coupled to an output node of the differential amplitude detection circuit for providing a signal representative of an amplitude of said differential input signal.
Claim 2
Dependent Claim
171 words
A differential amplitude detection circuit, comprising: a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal; a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal; a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component of said differential input signal; a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component of said differential input signal; and a summing circuit having first and second inputs respectively coupled for receiving said first and second peak signals and having an output coupled to an output node of the differential amplitude detection circuit for providing a signal representative of an amplitude of said differential input signal.
Claim 3
Dependent Claim
24 words
The differential amplitude detection circuit of claim 1, further comprising a first holding capacitor coupled to said output of said first peak detector circuit.
Claim 4
Dependent Claim
24 words
The differential amplitude detection circuit of claim 2, further comprising a second holding capacitor coupled to said output of said second peak detector circuit.
Claim 5
Dependent Claim
42 words
The differential amplitude detection circuit of claim 1, wherein said summing circuit comprises a first buffer amplifier having an input coupled for receiving said first peak signal and having an output coupled to said output node of the differential amplitude detection circuit.
Claim 6
Dependent Claim
35 words
The differential amplitude detection circuit of claim 4, wherein said summing circuit comprises a first resistor coupled between said output of said first buffer amplifier and said output node of the differential amplitude detection circuit.
Claim 7
Dependent Claim
42 words
The differential amplitude detection circuit of claim 1, wherein said summing circuit comprises a second buffer amplifier having an input coupled for receiving said second peak signal and having an output coupled to said output node of the differential amplitude detection circuit.
Claim 8
Dependent Claim
35 words
The differential amplitude detection circuit of claim 6, wherein said summing circuit comprises a second resistor coupled between said output of said second buffer amplifier and said output node of the differential amplitude detection circuit.
Claim 9
Dependent Claim
28 words
The differential amplitude detection circuit of claim 1, wherein: said first current load circuit comprises a third resistor; and said second current load circuit comprises a fourth resistor.
Claim 10
Dependent Claim
24 words
The differential amplitude detection circuit of claim 1, further comprising: circuit means for providing a common mode component signal of said differential input signal.
Claim 11
Dependent Claim
97 words
The differential amplitude detection circuit of claim 9, wherein said circuit means comprises: a first resistor having a first terminal coupled for receiving said first component of said differential input signal; a second resistor having a first terminal coupled for receiving said second component of said differential input signal and having a second terminal coupled to a second terminal of said first resistor; and a third buffer amplifier having an input coupled to said second terminals of said first and second resistors and having an output for providing a common mode component of said differential input signal.
Claim 12
Dependent Claim
70 words
The differential amplitude detection circuit of claim 10, further comprising a subtraction circuit having a first input coupled to said output of said summing circuit, a second input coupled to said output of said third buffer amplifier, and an output coupled to an output node for providing a signal representative of a difference between said output of said summing circuit and said common mode component of said differential input signal.
Claim 13
Dependent Claim
91 words
The differential amplitude detection circuit of claim 11, wherein said subtraction circuit includes: a third resistor coupled between said output node of said summing circuit of said differential amplitude detection circuit and a positive input of an amplifier having an output; a fourth resistor coupled between said output of said third buffer amplifier and a negative input of said amplifier; a fifth resistor coupled between said positive input of said amplifier and a power supply conductor; and a sixth resistor coupled between said output and said negative input of said amplifier.
Claim 14
Independent Claim
97 words
A method of detecting differential amplitude, including the steps of: storing a first peak amplitude of a first component of a differential input signal; storing a second peak amplitude of a second component of said differential input signal; tracking a decreasing offset component of said first component of said differential input signal with said first peak amplitude; tracking a decreasing offset component of said second component of said differential input signal with said second peak amplitude; and summing said first and second peak amplitudes for providing a signal representative of an amplitude of said differential input signal.
Claim 15
Independent Claim
97 words
A method of detecting differential amplitude, including the steps of: storing a first peak amplitude of a first component of a differential input signal; storing a second peak amplitude of a second component of said differential input signal; tracking a decreasing offset component of said first component of said differential input signal with said first peak amplitude; tracking a decreasing offset component of said second component of said differential input signal with said second peak amplitude; and summing said first and second peak amplitudes for providing a signal representative of an amplitude of said differential input signal.
Claim 16
Dependent Claim
25 words
The method of detecting differential amplitude of claim 13, further including the step of extracting a common mode component signal from said differential input signal.
Claim 17
Dependent Claim
32 words
The method of detecting differential amplitude of claim 14, further including the step of subtracting said common mode component signal from said signal representative of an amplitude of said differential input signal.
Claim 18
Dependent Claim
213 words
A differential amplitude detection circuit, comprising: a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal; a first holding capacitor coupled to said output of said first peak detector circuit; a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component; a first buffer amplifier having an input coupled for receiving said first peak signal and having an output; a first resistor coupled between said output of said first buffer amplifier and a first output node; a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal; a second holding capacitor coupled to said output of said second peak detector circuit; a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component; a second buffer amplifier having an input coupled for receiving said second peak signal and having an output; and a second resistor coupled between said output of said second buffer amplifier and said first output node.
Claim 19
Dependent Claim
213 words
A differential amplitude detection circuit, comprising: a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal; a first holding capacitor coupled to said output of said first peak detector circuit; a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component; a first buffer amplifier having an input coupled for receiving said first peak signal and having an output; a first resistor coupled between said output of said first buffer amplifier and a first output node; a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal; a second holding capacitor coupled to said output of said second peak detector circuit; a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component; a second buffer amplifier having an input coupled for receiving said second peak signal and having an output; and a second resistor coupled between said output of said second buffer amplifier and said first output node.
Claim 20
Dependent Claim
72 words
The differential amplitude detection circuit of claim 16, further comprising: a third resistor coupled between said input of said first peak detector circuit and an input of a third buffer amplifier; and a fourth resistor coupled between said input of said second peak detector circuit and said input of said third buffer amplifier, said third buffer amplifier having an output for providing a common mode component signal of said differential input signal.
Claim 21
Dependent Claim
69 words
The differential amplitude detection circuit of claim 17 further including a subtraction circuit having a first input coupled said first output node, a second input coupled to said output of said third buffer amplifier, and an output coupled to a second output node for providing a signal representative of a difference between said output of said first output node and said common mode component of said differential input signal.
Claim 22
Dependent Claim
97 words
The differential amplitude detection circuit of claim 18, wherein said subtraction circuit includes: an amplifier having a first input, a second input, and an output; a fifth resistor coupled between said first output node of the differential amplitude detection circuit and said first input of said amplifier; a sixth resistor coupled between said output of said third buffer amplifier and said second input of said amplifier; a seventh resistor coupled between said positive input of said amplifier and a power supply conductor; and an eighth resistor coupled between said output and said second input of said amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |