Bidirectional transceiver for high speed data system

Claim 2

A transceiver circuit connecting a fiber optic medium and a short data link comprising a coaxial conductor in a high speed data transmission network for simultaneously receiving and transmitting data over said coaxial conductor comprising: a transmitter section for receiving data from said fiber optic medium and for supplying a transmitted data signal; an impedance network coupled to said transmitter section and having first second and third output terminals, said impedance network receiving said transmitted data signal and providing a component of said transmitted data signal at said first output terminal connected to said coaxial conductor and providing a cancelling signal output having a component of said transmitted data signal at said second output terminal: said impedance network receiving a data signal over said coaxial conductor and providing a combined signal output having a component of said transmitted data signal and said received data signal at said third output terminal; a receiver section comprising a high speed subtracting circuit having a single stage subtracting transistor means with a first input terminal coupled with said second output terminal of said impedance network for receiving said cancelling signal output and a second input terminal coupled with said third output terminal of said impedance network for receiving said combined signal output and providing said received data signal as an output.

Claim 3

The transceiver circuit of claim 1, wherein said subtracting transistor has a small capacitance between its base and collector junction.

Claim 4

A pair of transceiver circuits for providing a link between a data unit and a fiber optic medium via a coaxial conductor in a high speed fiber optic data transmission network and for simultaneously receiving and transmitting data over said coaxial conductor comprising: first transmitter circuit means coupled with said fiber optic medium for receiving data therefrom and for supplying a first transmitted data signal; a first impedance network coupled to said first transmitter circuit means having first, second and third output terminals; said first impedance network receiving said first transmitted data signal and providing a component of said first transmitted data signal at said first output terminal connected to said coaxial conductor and providing a first cancelling signal output having a component of said first transmitted data signal at said second output terminal; said impedance network receiving a component of a second transmitted data signal over said coaxial conductor and providing a first combined signal output having a component of said first transmitted data signal and said second transmitted data signal at said third output terminal; first receiver circuit means including first high speed single stage subtracting transistor means having a first input terminal for receiving said first cancelling signal output and a second input terminal for receiving said first combined signal output and providing said component of said second transmitted data signal at an output terminal; second transmitter circuit means coupled with the data unit for receiving data therefrom and for supplying a second transmitted data signal; a second impedance network coupled to said second transmitter circuit means having first, second and third output terminals; said second impedance network receiving said second transmitted data signal and providing a component of said second transmitted data signal at said first output terminal connected to said coaxial conductor and providing a second cancelling signal output having a component of said transmitted data signal at said second output terminal; said second impedance network receiving said component of said first transmitted data signal over said coaxial conductor and providing a second combined signal output having a component of said second transmitted data signal and said first transmitted data signal at said third output terminal; and second receiver circuit means including second high speed single stage subtracting transistor means having a first input terminal for receiving said second cancelling signal output and a second input terminal for receiving said second combined signal output and providing said component of said first transmitted data signal at an output terminal.

Claim 5

A pair of transceiver circuits for providing a link between a data unit and a fiber optic medium via a coaxial conductor in a high speed fiber optic data transmission network and for simultaneously receiving and transmitting data over said coaxial conductor comprising: first transmitter circuit means coupled with said fiber optic medium for receiving data therefrom and for supplying a first transmitted data signal; a first impedance network coupled to said first transmitter circuit means having first, second and third output terminals; said first impedance network receiving said first transmitted data signal and providing a component of said first transmitted data signal at said first output terminal connected to said coaxial conductor and providing a first cancelling signal output having a component of said first transmitted data signal at said second output terminal; said impedance network receiving a component of a second transmitted data signal over said coaxial conductor and providing a first combined signal output having a component of said first transmitted data signal and said second transmitted data signal at said third output terminal; first receiver circuit means including first high speed single stage subtracting transistor means having a first input terminal for receiving said first cancelling signal output and a second input terminal for receiving said first combined signal output and providing said component of said second transmitted data signal at an output terminal; second transmitter circuit means coupled with the data unit for receiving data therefrom and for supplying a second transmitted data signal; a second impedance network coupled to said second transmitter circuit means having first, second and third output terminals; said second impedance network receiving said second transmitted data signal and providing a component of said second transmitted data signal at said first output terminal connected to said coaxial conductor and providing a second cancelling signal output having a component of said transmitted data signal at said second output terminal; said second impedance network receiving said component of said first transmitted data signal over said coaxial conductor and providing a second combined signal output having a component of said second transmitted data signal and said first transmitted data signal at said third output terminal; and second receiver circuit means including second high speed single stage subtracting transistor means having a first input terminal for receiving said second cancelling signal output and a second input terminal for receiving said second combined signal output and providing said component of said first transmitted data signal at an output terminal.

Claim 6

A pair of transceiver circuits for providing a link between a data unit and a fiber optic medium via a coaxial conductor in a high speed fiber optic data transmission network and for simultaneously receiving and transmitting data over said coaxial conductor comprising: first transmitter circuit means coupled with the fiber optic medium for receiving data therefrom and for supplying a first transmitted data signal; first equalizing circuit means receiving said first transmitted data signal from said first transmitter circuit means and providing a first equalized transmitted data signal; a first impedance network coupled to said first equalizing circuit means having first, second and third output terminals; said first impedance network receiving said first equalized transmitted data signal and providing a component of said first equalized transmitted data signal at said first output terminal connected to said coaxial conductor and providing a first cancelling signal output having a component of said first equalized transmitted data signal at said second output terminal; said impedance network receiving a component of a second equalized transmitted data signal over said coaxial conductor and providing a combined signal output having a component of said first equalized transmitted data signal and said second equalized transmitted data signal at said third output terminal; first receiver circuit means including first high speed single stage subtracting transistor means having a first input terminal for receiving said first cancelling signal output and a second input terminal for receiving said first combined signal output and providing said component of said second equalized transmitted data signal at an output terminal; second equalizing circuit means coupled with said output terminal of said first transistor for receiving said component of said second equalized transmitted data signal from said first subtracting transistor means and providing a first equalized output data signal; second transmitter circuit means coupled with the data unit for receiving data therefrom and for supplying a second transmitted data signal; third equalizing circuit means for receiving said second transmitted data signal from said second transmitter circuit means and providing said second equalized transmitted data signal; a second impedance network coupled to said second equalized transmitted data signal and having first, second and third output terminals; said second impedance network receiving said second equalized transmitted data signal and providing a component of said second equalized transmitted data signal at said first output terminal connected to said coaxial conductor and providing a second cancelling signal output having a component of said second equalized transmitted data signal at said second output terminal; said second impedance network receiving said component of said equalized first transmitted data signal over said coaxial conductor and providing a second combined signal output having a component of said second equalized transmitted data signal at said third output terminal; second receiver circuit means including second high speed single stage subtracting transistor means having a first input terminal for receiving said second cancelling signal output and a second input terminal for receiving said second combined signal output and providing said first equalized transmitted data signal at an output terminal; fourth equalizing circuit means coupled with said output terminal of said second transistor for receiving a component of said first equalized transmitted received data signal from second subtracting transistor means and providing a second equalized output data signal to the data unit.

Claim 7

A pair of transceiver circuits for providing a link between a data unit and a fiber optic medium via a coaxial conductor in a high speed fiber optic data transmission network and for simultaneously receiving and transmitting data over said coaxial conductor comprising: first transmitter circuit means coupled with the fiber optic medium for receiving data therefrom and for supplying a first transmitted data signal; first equalizing circuit means receiving said first transmitted data signal from said first transmitter circuit means and providing a first equalized transmitted data signal; a first impedance network coupled to said first equalizing circuit means having first, second and third output terminals; said first impedance network receiving said first equalized transmitted data signal and providing a component of said first equalized transmitted data signal at said first output terminal connected to said coaxial conductor and providing a first cancelling signal output having a component of said first equalized transmitted data signal at said second output terminal; said impedance network receiving a component of a second equalized transmitted data signal over said coaxial conductor and providing a combined signal output having a component of said first equalized transmitted data signal and said second equalized transmitted data signal at said third output terminal; first receiver circuit means including first high speed single stage subtracting transistor means having a first input terminal for receiving said first cancelling signal output and a second input terminal for receiving said first combined signal output and providing said component of said second equalized transmitted data signal at an output terminal; second equalizing circuit means coupled with said output terminal of said first transistor for receiving said component of said second equalized transmitted data signal from said first subtracting transistor means and providing a first equalized output data signal; second transmitter circuit means coupled with the data unit for receiving data therefrom and for supplying a second transmitted data signal; third equalizing circuit means for receiving said second transmitted data signal from said second transmitter circuit means and providing said second equalized transmitted data signal; a second impedance network coupled to said second equalized transmitted data signal and having first, second and third output terminals; said second impedance network receiving said second equalized transmitted data signal and providing a component of said second equalized transmitted data signal at said first output terminal connected to said coaxial conductor and providing a second cancelling signal output having a component of said second equalized transmitted data signal at said second output terminal; said second impedance network receiving said component of said equalized first transmitted data signal over said coaxial conductor and providing a second combined signal output having a component of said second equalized transmitted data signal at said third output terminal; second receiver circuit means including second high speed single stage subtracting transistor means having a first input terminal for receiving said second cancelling signal output and a second input terminal for receiving said second combined signal output and providing said first equalized transmitted data signal at an output terminal; fourth equalizing circuit means coupled with said output terminal of said second transistor for receiving a component of said first equalized transmitted received data signal from second subtracting transistor means and providing a second equalized output data signal to the data unit.