Patent US5491105A successfully refreshed from Google Patents.
US5491105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
LDMOS transistor with self-aligned source/backgate and photo-aligned gate
Assignee: Texas Instruments Inc
•
Filing: 1994-09-09
•
Granted: 1996-02-13
•
Expires: 2014-09-09
Abstract
Abstract An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).
Inventors
- 👤 Michael C. Smayling
- 👤 Manuel L. Torreno, Jr., deceased
- 👤 Georges Falessi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D10/00; H10D10/60; H10D30/01; H10D30/021; H10D30/028; H10D30/0281; H10D30/0285; H10D30/0291; H10D30/66; H10D30/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0142; H10D84/02; H10D84/03; H10D84/038; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D62/152; H10D62/153; H10D62/156; H10D62/157; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/151
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
164 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into each said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a D-well region of a lateral DMOS device which includes a source and a backgate, wherein said first doped region comprises said source and said second doped region comprises said backgate.
Claim 2
Independent Claim
164 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into each said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a D-well region of a lateral DMOS device which includes a source and a backgate, wherein said first doped region comprises said source and said second doped region comprises said backgate.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said dopants of a first conductivity type comprise n-type dopants and said dopants of a second conductivity type comprise p-type dopants.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein said n-type dopants comprise arsenic dopants and said p-type dopants comprise boron dopants.
Claim 5
Dependent Claim
22 words
The method of claim 1 and further comprising the step of forming a gate structure adjacent to and partially overlapping said backgate.
Claim 6
Dependent Claim
35 words
The method of claim 4 and further comprising the step of forming first and second source/drain regions in said semiconductor layer, said first and second source/drain regions formed adjacent opposite ends of said gate structure.
Claim 7
Independent Claim
151 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into each said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a D-well region of a vertical DMOS device; said D-well region comprising said first and second doped regions.
Claim 8
Independent Claim
151 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into each said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a D-well region of a vertical DMOS device; said D-well region comprising said first and second doped regions.
Claim 9
Independent Claim
145 words
A method of forming a circuit device in a semiconductor layer comprising the steps of; exposing a region of said semiconductor layer; implanting p-type dopants into said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a bipolar transistor, said bipolar transistor comprising said first and second doped regions.
Claim 10
Independent Claim
145 words
A method of forming a circuit device in a semiconductor layer comprising the steps of; exposing a region of said semiconductor layer; implanting p-type dopants into said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a bipolar transistor, said bipolar transistor comprising said first and second doped regions.
Claim 11
Dependent Claim
37 words
The method of claim 7 wherein said circuit device comprises an NPN transistor which includes an emitter and a base and wherein said first doped region comprises said emitter and said second doped region comprises said base.
Claim 12
Independent Claim
152 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a Zener diode which includes an anode and a cathode, said Zener diode comprising said first and second doped regions.
Claim 13
Independent Claim
152 words
A method of forming a circuit device in a semiconductor layer comprising the steps of: exposing a region of said semiconductor layer; implanting p-type dopants into said exposed region of said semiconductor layer, said p-type dopants having a first diffusion rate; implanting n-type dopants into said exposed region of said semiconductor layer, said n-type dopants having a second diffusion rate, said second diffusion rate different than said first diffusion rate; and heating said exposed region such that a first doped region is formed within a second doped region wherein said first doped region is doped with dopants of a first conductivity type and said second doped region is doped with dopants of a second conductivity type, said first conductivity type being different than said second conductivity type; wherein said circuit device comprises a Zener diode which includes an anode and a cathode, said Zener diode comprising said first and second doped regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |