US5491100A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a semiconductor device having a contact window structure
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-11-23
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Granted: 1996-02-13
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Expires: 2013-11-23
Abstract
Abstract A method of manufacturing and a structure of a semiconductor device is disclosed whereby a gate insulating layer, a polycrystalline silicon layer, a tungsten silicide layer and a first insulating layer are formed on a semiconductor substrate. Gates are formed by the removal of the layers by dry etching, wherein the etch rate of the tungsten silicide layer is faster than the other layers, thereby forming an undercut region in the tungsten silicide layer. A second insulating layer is formed on the surface of the resultant structure to form spacers, and a contact window is formed between the gates via an etching process. The second insulating layer portion which forms the spacers need not be thick to prevent etching of the gates when forming the contact window, therefore good step coverage is achieved and reliability of the device is increased.
Inventors
- 👤 Yong H. Lee
- 👤 Young W. Seo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:40
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/28; H10P50/282; H10P50/283; H10P50/71; H10P50/73; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
149 words
A method for manufacturing a gate structure of a semiconductor device comprising the steps of: forming a gate insulating layer on a semiconductor substrate; forming a first conductive layer of polycrystalline silicon on said gate insulating layer; forming a second conductive layer of refractory metal silicide on said first conductive layer; forming a first insulating layer on said second conductive layer; forming a first photoresist pattern on said first insulating layer; forming a gate structure in said first insulating layer, said second conductive layer, and said first conductor layer by removing an exposed portion of said first insulating layer, said second conductive layer, and said first conductive layer using said first photoresist pattern as a mask, said second conductive layer of said gate structure having a recessed edge portion with respect to an edge portion of said first insulating layer and an edge portion of said first conductive layer.
Claim 2
Independent Claim
149 words
A method for manufacturing a gate structure of a semiconductor device comprising the steps of: forming a gate insulating layer on a semiconductor substrate; forming a first conductive layer of polycrystalline silicon on said gate insulating layer; forming a second conductive layer of refractory metal silicide on said first conductive layer; forming a first insulating layer on said second conductive layer; forming a first photoresist pattern on said first insulating layer; forming a gate structure in said first insulating layer, said second conductive layer, and said first conductor layer by removing an exposed portion of said first insulating layer, said second conductive layer, and said first conductive layer using said first photoresist pattern as a mask, said second conductive layer of said gate structure having a recessed edge portion with respect to an edge portion of said first insulating layer and an edge portion of said first conductive layer.
Claim 3
Dependent Claim
60 words
A method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second insulating layer on said gate structure and removing a portion of said second insulating layer to form a sidewall at least on said edge portion of said recessed second conductive layer and on said edge portion of said first conductive layer.
Claim 4
Dependent Claim
52 words
A method for manufacturing a semiconductor device according to claim 1, wherein said step of forming a gate structure includes a step of removing said second conductive layer at a faster rate than said first insulating layer and said first conductive layer to enlarge said recessed portion in said second conductive layer.
Claim 5
Dependent Claim
43 words
A method for manufacturing a semiconductor device according to claim 1, wherein said portions of said first insulating layer, said second conductive layer, and said first conductive layer are removed by a dry etching method comprising SF 6 gas and Cl 2 gas.
Claim 6
Dependent Claim
30 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first conductive layer is etched by a dry etching method comprising HBr gas and Cl 2 gas.
Claim 7
Dependent Claim
22 words
A method for manufacturing a semiconductor device according to claim 2, wherein said second insulating layer is etched by an etch-back process.
Claim 8
Dependent Claim
53 words
A method for manufacturing a semiconductor device according to claim 1, further comprising the step of enlarging said recessed portion in said second conductive layer of said gate structure by using a wet solution composed of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O).
Claim 9
Dependent Claim
86 words
A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: forming a source and a drain by ion-implanting an N-type impurity into said semiconductor substrate adjacent to said gate structure; forming a second insulating layer on said source, said drain and said gate structure; forming a second photoresist pattern on said second insulating layer; and forming a spacer adjacent to said gate structure by removing a portion of said second insulating layer which is exposed by said second photoresist pattern.
Claim 10
Dependent Claim
44 words
A method for manufacturing a semiconductor device according to claim 1, wherein said second conductive layer is provided to have an etch rate which is faster than an etch rate of said first conductive layer and an etch rate of said gate insulating layer.
Claim 11
Dependent Claim
33 words
A method for manufacturing a semiconductor device according to claim 9, wherein said first insulating layer is provided to have an etch rate slower than said etch rate of said second conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |