EP0497596A2
Expired / Lapsed
EP
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Method for fabricating integrated circuit structures
Assignee: STMicroelectronics lnc USA
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Filing: 1992-01-30
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Granted: —
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Expires: 2012-01-30
Abstract
Abstract Polycrystalline silicon interconnect elements are formed using a sandwich of a highly conductive silicide layer between two polycrystalline silicon layers. Transistors and active areas are defined using standard techniques. A layer of refractory metal is deposited over the integrated circuit device, and heated to form a silicide with exposed monocrystalline and polycrystalline silicon areas. The depth of the silicon formed is not very large, and is consistent with protecting shallow junctions in the active areas of the device. Sheet resistance of the polycrystalline silicon conductive elements is maintained at low levels by the additional silicide layer within the sandwich.
Inventors
- 👤 Fu-Tai Liou
- 👤 Che-Chia Wei
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 11:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
91 words
A method for forming a conductive structure on an integrated circuit, comprising the steps of: forming a first polycrystalline silicon layer; forming a first conductive silicide layer over the first polycrystalline silicon layer; forming a second polycrystalline silicon layer over the first conductive silicide layer; patterning the first and second polycrystalline silicon layers and the first conductive silicide layer to define a conducting element; and simultaneously converting at least a portion of the second polycrystalline silicon layer and a portion of a third conductive silicon region to a second conductive silicide.
Claim 2
Dependent Claim
44 words
The method of claim 1, wherein said converting step comprises the steps of: depositing a refractory metal over the surface of the integrated circuit; heating the integrated circuit to cause the refractory metal to react with underlying silicon; and removing any unreacted refractory metal.
Claim 3
Dependent Claim
21 words
The method of claim 2, wherein the refractory metal comprises titanium, and wherein the first conductive silicide layer comprises tungsten silicide.
Claim 4
Dependent Claim
39 words
The method of claim 1, further comprising the step of: before said first polycrystalline silicon layer forming step; forming a gate oxide layer over the integrated circuit, wherein the conducting element defines a gate for a field effect device.
Claim 5
Dependent Claim
51 words
The method of claim 4, wherein said patterning step exposes regions of a substrate underlying the gate oxide layer, and further comprising the steps of: after said patterning step, implanting impurities into the substrate to form lightly doped drain regions; and forming sidewall oxide regions alongside vertical sides of the gate.
Claim 6
Dependent Claim
39 words
The method of claim 5, further comprising the step of: implanting impurities into the substrate to form source/drain regions for the field effect device, the implanting being after said sidewall oxide regions forming step or after said converting step.
Claim 7
Dependent Claim
16 words
The method of claim 1, wherein the first and second conductive silicides comprise refractory metal silicides.
Claim 8
Dependent Claim
20 words
The method of claim 7, wherein the first and second conductive silicides are conductive metal silicides containing different refractory metals.
Claim 9
Dependent Claim
24 words
The method of claim 1, wherein the third conductive silicon region comprises a region in a substrate and comprises a conductor containing polycrystalline silicon.
Claim 10
Dependent Claim
99 words
A structure consisting of a portion of a semiconductor integrated circuit comprising: a first conductive region having a conductive silicide layer thereon which has a first thickness; and a conducting element having a first polycrystalline silicon layer, a first conducting silicide layer on the first polycrystalline silicon layer, a second polycrystalline silicon layer on the first conducting silicide layer, and a second conducting silicide layer on the second polycrystalline silicon layer, wherein the second conducting silicide layer has substantially the first thickness and is formed from the same material as the conductive silicide layer on the first conductive region.
Claim 11
Dependent Claim
17 words
The structure of claim 10, wherein the conducting element defines a gate for a field effect device.
Claim 12
Dependent Claim
15 words
The structure of claim 11, has sidewall oxide spacers on vertical sides of the gate.
Claim 13
Dependent Claim
47 words
The structure of claim 12, further comprising: second conductive region having a conductive silicide layer thereon which has a first thickness; wherein said first and second conductive regions define active regions in a substrate, and are spaced on opposite sides of the gate to define source/drain regions.
Claim 14
Dependent Claim
24 words
The structure of claim 10, wherein said first conductive region lies in a substrate and defines a conductive path between two field effect devices.
Claim 15
Dependent Claim
27 words
The structure of claim 14, further comprising: a conducting polycrystalline silicon interconnect element which crosses said first conductive region, and is separated therefrom by an insulating layer.
References Cited (Backward Citations)
No citation records indexed.
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