Semiconductor memory device including a component having improved breakdown voltage characteristics

Claim 2

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein each of said memory cells comprises an insulating gate type field effect transistor, a plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, a plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, and wherein each of said plurality of capacitive elements is formed by an insulating gate type field effect transistor having an insulating film identical in thickness to that of the transistor of said memory cell.

Claim 3

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, a plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, further comprising a voltage-down circuit for down-converting an externally applied power supply voltage for generating an internal power supply voltage, wherein each of said plurality of capacitive elements is formed by an insulating gate type field effect transistor having an insulating film identical in thickness to that of an insulating gate type field effect transistor included in a circuit to which said internal power supply voltage is applied.

Claim 4

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, a plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, further comprising a voltage-down circuit for down-converting an externally applied power supply voltage for generating an internal power supply voltage, wherein each of said plurality of capacitive elements is formed by an insulating gate type field effect transistor having an insulating film identical in thickness to that of an insulating gate type field effect transistor included in a circuit to which said internal power supply voltage is applied.

Claim 5

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, a plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, wherein said word line driving means includes an insulated gate type field effect transistor as a component, and wherein each of said capacitive elements is formed of an insulated gate type field effect transistor having a gate insulating film identical in thickness to that of the insulated gate type field effect transistor included in said word line driving means.

Claim 6

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, a plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, wherein said word line driving means includes an insulated gate type field effect transistor as a component, and wherein each of said capacitive elements is formed of an insulated gate type field effect transistor having a gate insulating film identical in thickness to that of the insulated gate type field effect transistor included in said word line driving means.

Claim 7

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, further comprising array driving means including an insulated gate type field effect transistor and coupled to said memory cell array for transmitting a driving signal directly to said memory array, and wherein each of said capacitive elements is formed by an insulating gate type field effect transistor having a gate insulating film identical in thickness to that of the transistor included in said array driving means.

Claim 8

The semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines, each having a row of memory cells connected, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage applied to a first power supply node to generate a high voltage, word line driving means responsive to a word line selecting signal from said word line selecting means for transmitting a high voltage generated by said boosting means to a selected word line, plurality of capacitive elements connected in series between an output node of said boosting means and a second power supply voltage node, further comprising array driving means including an insulated gate type field effect transistor and coupled to said memory cell array for transmitting a driving signal directly to said memory array, and wherein each of said capacitive elements is formed by an insulating gate type field effect transistor having a gate insulating film identical in thickness to that of the transistor included in said array driving means.

Claim 9

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and column, a plurality of word lines, each having a row of memory cells connected thereto, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage for generating a high voltage, word line driving means responsive to the word line selecting signal from said word line selecting means for transmitting the high voltage generated by said boosting means on the selected word line, a first circuit formed of an insulating gate type field effect transistor, and directly connected to an external terminal for carrying out input/output of a signal with an external device, a capacitive element formed of an insulating gate type field effect transistor having an insulating film identical in thickness to that of a gate insulating film of said insulating gate type field effect transistor of said first circuit, and provided between an output node of said boosting means and a second power supply voltage source.

Claim 10

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and column, a plurality of word lines, each having a row of memory cells connected thereto, word line selecting means responsive to an address signal for generating a word line selecting signal to select a word line of said plurality of word lines, boosting means for boosting a first power supply voltage for generating a high voltage, word line driving means responsive to the word line selecting signal from said word line selecting means for transmitting the high voltage generated by said boosting means on the selected word line, a first circuit formed of an insulating gate type field effect transistor, and directly connected to an external terminal for carrying out input/output of a signal with an external device, a capacitive element formed of an insulating gate type field effect transistor having an insulating film identical in thickness to that of a gate insulating film of said insulating gate type field effect transistor of said first circuit, and provided between an output node of said boosting means and a second power supply voltage source.

Claim 11

A semiconductor memory device including an external terminal receiving an external signal and operating with an power supply voltage comprising: a first inverter connected to directly receive said external signal applied at said external terminal, and including an insulated gate type field effect transistor having a gate insulation film of a first thickness; a second inverter coupled to receive an output of said first inverter for generating an internal signal, and including an insulated gate type field effect transistor, having a gate insulation film of a second thickness smaller than said first thickness; high voltage generator responsive to a clock signal for boosting said power supply voltage to generate a high voltage at an output node; and a capacitor element coupled to said output node, for stabilizing said high voltage, and being formed of an insulated gate type field effect transistor having a gate insulating film of said first thickness.

Claim 12

A semiconductor memory device including an external terminal receiving an external signal and operating with an power supply voltage comprising: a first inverter connected to directly receive said external signal applied at said external terminal, and including an insulated gate type field effect transistor having a gate insulation film of a first thickness; a second inverter coupled to receive an output of said first inverter for generating an internal signal, and including an insulated gate type field effect transistor, having a gate insulation film of a second thickness smaller than said first thickness; high voltage generator responsive to a clock signal for boosting said power supply voltage to generate a high voltage at an output node; and a capacitor element coupled to said output node, for stabilizing said high voltage, and being formed of an insulated gate type field effect transistor having a gate insulating film of said first thickness.

Claim 13

The semiconductor memory device according to claim 6, further including a voltage-down converter for down-converting an external power supply voltage to generate said power supply voltage, and wherein said first and second inverters operate with said external power supply voltage as an operating power supply voltage.

Claim 14

A semiconductor memory device including an external terminal for supply an external signal and operating with a power supply voltage, comprising: a first inverter including an insulated gate type field effect transistor having a gate insulation film of a first thickness, for receiving an internal signal from an internal circuit; a second inverter directly connected to said external terminal and responsive to an output of said first inverter for driving said output, and including an insulating gate type field effect transistor having a gate insulation film of a second thickness greater than said first thickness; high voltage generator responsive to a clock signal for boosting the power supply voltage to generate a high voltage at an output node; and a capacitor element connected to said output node for stabilizing said high voltage, and including an insulated gate type field effect transistor having a gate insulation film of said second thickness.

Claim 15

A semiconductor memory device including an external terminal for supply an external signal and operating with a power supply voltage, comprising: a first inverter including an insulated gate type field effect transistor having a gate insulation film of a first thickness, for receiving an internal signal from an internal circuit; a second inverter directly connected to said external terminal and responsive to an output of said first inverter for driving said output, and including an insulating gate type field effect transistor having a gate insulation film of a second thickness greater than said first thickness; high voltage generator responsive to a clock signal for boosting the power supply voltage to generate a high voltage at an output node; and a capacitor element connected to said output node for stabilizing said high voltage, and including an insulated gate type field effect transistor having a gate insulation film of said second thickness.

Claim 16

The semiconductor memory device according to the claim 8, further including a voltage-down converter for down-converting an externally applied power supply voltage to generate said power supply voltage, and wherein said externally applied power supply voltage is applied to said first and second inverters as an operating power supply voltage.