Word line drive circuit

Claim 2

A drive circuit comprising a first FET and a second FET which are connected in series and between a first power supply terminal and a second power supply terminal, a junction of said first FET and said second FET being connected to an output terminal which provides a drive signal, and said first FET having an opposite conductivity to said second FET, a boosting capacitor having a first electrode connected to a gate of said first FET and a second electrode connected to a first node to which a first control signal is supplied, and drive means which generates a second control signal and supplies said second control signal to said gate of said first FET, said first control signal and said second control signal having a substantially inverse phase to the phase of said drive signal.

Claim 3

A drive circuit according to claim 1 further comprising a third FET and a fourth FET which are connected in series and between a third power supply terminal and said second power supply terminal, which supply said first control signal to said first node, and which have the same conductivity as said second FET.

Claim 4

A drive circuit according to claim 2 wherein said drive means further comprises a pair of FETs which are connected between said third power supply terminal and said second power supply terminal, and have the same conductivity as said second FET.

Claim 5

A word line drive circuit for a random access memory to provide a drive signal having a voltage greater than a voltage V supplied from an external power supply for said circuit, said circuit comprising a first power supply terminal and a second power supply terminal, means providing said first power supply terminal with a voltage greater than the voltage supplied from an external power supply, a first FET and a second FET which are connected in series and between said first power supply terminal and said second power supply terminal, a junction of said first FET and said second FET being connected to an output terminal at which said drive signal is produced and said first FET having an opposite conductivity to said second FET, a boosting capacitor having a first electrode connected to a gate of said first FET and a second electrode connected to a node to which a first control signal having a substantially inverse phase to that of said drive signal is supplied, and drive means which supplies a second control signal to said gate of said first FET, said second control signal having the same phase as that of said first control signal, and a voltage of said second control signal being increased by said boosting capacitor to a level sufficient to keep said first FET nonconductive.

Claim 6

A word line drive circuit for a random access memory to provide a drive signal having a voltage greater than a voltage V supplied from an external power supply for said circuit, said circuit comprising a first power supply terminal and a second power supply terminal, means providing said first power supply terminal with a voltage greater than the voltage supplied from an external power supply, a first FET and a second FET which are connected in series and between said first power supply terminal and said second power supply terminal, a junction of said first FET and said second FET being connected to an output terminal at which said drive signal is produced and said first FET having an opposite conductivity to said second FET, a boosting capacitor having a first electrode connected to a gate of said first FET and a second electrode connected to a node to which a first control signal having a substantially inverse phase to that of said drive signal is supplied, and drive means which supplies a second control signal to said gate of said first FET, said second control signal having the same phase as that of said first control signal, and a voltage of said second control signal being increased by said boosting capacitor to a level sufficient to keep said first FET nonconductive.

Claim 7

A word line drive circuit according to claim 4 further comprising means supplying a third control signal to a gate of said second FET to keep said second FET nonconductive while the word line drive signal is to be produced.

Claim 8

A word line drive circuit according to claim 4 further comprising a third FET and a fourth FET which are connected in series and between a third power supply terminal connected to said external power supply and said second source terminal, a junction of said third FET and said fourth FET being connected to said node to supply said first control signal.

Claim 9

A word line drive circuit according to claim 6 wherein said third FET and said fourth FET have the same conductivity as said second FET.

Claim 10

A word line drive circuit according to claim 7 wherein said third FET is connected to receive, at its gate, said second control signal, and said fourth FET is connected to receive, at its gate, a delayed signal which has an inverse phase, with a certain delay, to that of said second signal.

Claim 11

A word line drive circuit according to claim 4 wherein said drive means comprises a pair of FETs which are connected in series and between said third source terminal connected to an external power supply and said second source terminal, a junction between said pair of FETs being connected to said gate of said first FET to supply said first control signal.

Claim 12

A word line drive circuit according to claim 9 wherein said pair of FETs have the same conductivity as said second FET.

Claim 13

A word line drive circuit according to claim 4 wherein said third control signal has the same phase, with a certain dealy, as that of said second signal.