US4980799A
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US
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Electrostatic capacity device in semiconductor memory device, and apparatus for and method of driving sense amplifier using electrostatic capacity device
Assignee: DRAM MEMORY TECHNOLOGIES LLC
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Filing: 1990-01-04
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Granted: 1990-12-25
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Expires: 2010-01-04
Abstract
Abstract An apparatus (50) activates and drives sense amplifiers in a dynamic random access memory (DRAM) at a high speed. The sense amplifier includes a P-MOS sense amplifier (15, 16) and an n-MOS sense amplifier (18, 19). The P-MOS sense amplifier is connected to a power line (31) through a first switching element (22) to be activated while the n-MOS sense amplifier is connected to a ground line (30) through a second switching element (20) to be activated. The sense amplifier driving apparatus includes a capacitor (34) conneced between the power line and the ground line. This enables compensation for the charge and discharge currents which flow in the bit line charging and discharging operations, reduction in the bit line charging and discharging times, and suppression of the fluctuation in supply potential, improving the operating speed of the DRAM. This capacitor (34) has an electrode and a dielectric which are made of the same materials with those of a memory cell capacitor (6) comprised in a memory cell, and the dielectric is formed to be of the same film thickness also as that of the memory cell capacitor. The memory cell has a stack-type structure, where the capacitor comprises at least two capacitance elements connected in series.
Inventors
- 👤 Youichi Tobita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
333 words
A sense amplifier driving apparatus in a semiconductor memory device having a plurality of memory cells (1) arranged in a matrix of rows and columns and each comprising one field effect transistor (5) and one capacitor (6)',a plurality of bit line pairs (BL and BL; 2 and 7) each having connected thereto one column of said plurality of memory cells, and a plurality of sense amplifiers (50) provided to each of said plurality of bit line pairs to detect and differentially amplify potential on the corresponding bit line pair, comprising: a first signal line (14) coupled to each of said plurality of sense amplifiers for transmitting a first sense amplifier driving signal (φ A ); a second signal line (17) coupled to each of said plurality of sense amplifiers for transmitting a second sense amplifier driving signal (φ B ); a first power line (31) for transmitting a first supply potential; a second power line (30) for transmitting a second supply potential; a first switching means (22) provided between said first signal line and said first power line to be responsive to a first sense amplifier activating timing signal (φ S ) for connecting said first signal line with said first power line; a second switching means (25) provided between said second signal line and said second power line to be responsive to a second sense amplifier activating timing signal for connecting said second signal line with said second power line; and capacitance means (34) having one electrode connected to said first power line and the other electrode connected to said second power line, and comprising at least one capacitance element (C; C20, C30), said capacitance element having an electrode (106, 105) and a dielectric (107) which are made of the same materials as those of said capacitor (6) comprised in said memory cell, and the dielectric (107b to 107h) of said capacitance element having the same film thickness as that of a dielectric (107a) of the capacitor comprised in said memory cell.
Claim 2
Dependent Claim
333 words
A sense amplifier driving apparatus in a semiconductor memory device having a plurality of memory cells (1) arranged in a matrix of rows and columns and each comprising one field effect transistor (5) and one capacitor (6)',a plurality of bit line pairs (BL and BL; 2 and 7) each having connected thereto one column of said plurality of memory cells, and a plurality of sense amplifiers (50) provided to each of said plurality of bit line pairs to detect and differentially amplify potential on the corresponding bit line pair, comprising: a first signal line (14) coupled to each of said plurality of sense amplifiers for transmitting a first sense amplifier driving signal (φ A ); a second signal line (17) coupled to each of said plurality of sense amplifiers for transmitting a second sense amplifier driving signal (φ B ); a first power line (31) for transmitting a first supply potential; a second power line (30) for transmitting a second supply potential; a first switching means (22) provided between said first signal line and said first power line to be responsive to a first sense amplifier activating timing signal (φ S ) for connecting said first signal line with said first power line; a second switching means (25) provided between said second signal line and said second power line to be responsive to a second sense amplifier activating timing signal for connecting said second signal line with said second power line; and capacitance means (34) having one electrode connected to said first power line and the other electrode connected to said second power line, and comprising at least one capacitance element (C; C20, C30), said capacitance element having an electrode (106, 105) and a dielectric (107) which are made of the same materials as those of said capacitor (6) comprised in said memory cell, and the dielectric (107b to 107h) of said capacitance element having the same film thickness as that of a dielectric (107a) of the capacitor comprised in said memory cell.
Claim 3
Dependent Claim
32 words
The driving apparatus according to claim 1, wherein said capacitance means comprises the capacitance element which is provided in a position as near as possible to said first and second switching means.
Claim 4
Dependent Claim
20 words
The driving apparatus according to claim 1, wherein said capacitance element of said capacitance means comprises an MOS capacitor structure.
Claim 5
Dependent Claim
59 words
The driving apparatus according to claim 1, wherein said memory cell capacitor has a stack structure in which both of the two electrodes are formed on a semiconductor substrate together, and said capacitance means comprises at least two capacitance elements connected in series, these capacitance elements being manufactured in the same process as that of said memory cell capacitor.
Claim 6
Dependent Claim
243 words
A sense amplifier driving method in a semiconductor memory device having a plurality of memory cells arranged in a matrix of rows and columns and each storing information, a plurality of bit line pairs each having connected thereto one column of said plurality of memory cells and transmitting data having been held in selected memory cells, and a plurality of sense amplifiers provided to each of said plurality of bit line pairs to amplify potential difference on the corresponding bit line pair, comprising the steps of: activating said sense amplifiers, said activating step comprising the steps of electrically connecting a first signal line (14) with a first power line (31), and electrically connecting a second signal line (17) with a second power line (30), said first signal line and said first power line charging one bit line of said respective bit line pairs through said sense amplifiers, and said second signal line and said second power line discharging the other bit line of said respective bit line pairs through said sense amplifiers; and reducing current flowing into said second power line by shunting current flowing from said second signal line to said second power line with the use of a capacitor provided between said first power line and said second power line to be connected to both of them, and making current from said second power line and current from said capacitor merged into one to be transmitted to said first signal line.
Claim 7
Dependent Claim
243 words
A sense amplifier driving method in a semiconductor memory device having a plurality of memory cells arranged in a matrix of rows and columns and each storing information, a plurality of bit line pairs each having connected thereto one column of said plurality of memory cells and transmitting data having been held in selected memory cells, and a plurality of sense amplifiers provided to each of said plurality of bit line pairs to amplify potential difference on the corresponding bit line pair, comprising the steps of: activating said sense amplifiers, said activating step comprising the steps of electrically connecting a first signal line (14) with a first power line (31), and electrically connecting a second signal line (17) with a second power line (30), said first signal line and said first power line charging one bit line of said respective bit line pairs through said sense amplifiers, and said second signal line and said second power line discharging the other bit line of said respective bit line pairs through said sense amplifiers; and reducing current flowing into said second power line by shunting current flowing from said second signal line to said second power line with the use of a capacitor provided between said first power line and said second power line to be connected to both of them, and making current from said second power line and current from said capacitor merged into one to be transmitted to said first signal line.
Claim 8
Dependent Claim
38 words
The method according to claim 5, wherein said activating step comprises a step of simultaneously making electrical connections between said first signal line and said first power line, and said second signal line and said second power line.
Claim 9
Dependent Claim
75 words
A capacitance means (34; C) used in a semiconductor memory device having a plurality of memory cells (1) each comprising one switching transistor (5) and one capacitor (6), comprising: an electrode (103; 106 and 107) made of the same material as an electrode comprised in said memory cell capacitor (6); and a dielectric layer (104; 107) being the same in material and film thickness as a dielectric layer comprised in said memory cell capacitor (6).
Claim 10
Dependent Claim
75 words
A capacitance means (34; C) used in a semiconductor memory device having a plurality of memory cells (1) each comprising one switching transistor (5) and one capacitor (6), comprising: an electrode (103; 106 and 107) made of the same material as an electrode comprised in said memory cell capacitor (6); and a dielectric layer (104; 107) being the same in material and film thickness as a dielectric layer comprised in said memory cell capacitor (6).
Claim 11
Dependent Claim
60 words
The capacitance means according to claim 7, wherein said memory cell capacitor has an MOS structure having one electrode formed of a conductive layer and the other electrode formed of a semiconductor layer, and said capacitance means further comprises a capacitor (101', 102, 103, 104) of an MOS structure formed in the same manufacturing process with said memory cell capacitor.
Claim 12
Dependent Claim
69 words
The capacitance means according to claim 7, wherein said memory cell capacitor has a stack structure having one and the other electrodes formed of conductive layers which have been formed on a semiconductor substrate together, and said capacitance means comprises at least two capacitance elements (C20, C30; C; 105, 106 and 107) connected in series and each having been formed in the same process with said memory cell capacitor.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |