Multi-port memory device with multiple sets of columns

Claim 1

A multi-port memory comprising: a. a dynamic random access memory array, the array comprising a first, a second, and a third set of columns each column comprising a sense amplifier, the first set comprising a predetermined number of columns, the second and the third set comprising the predetermined number of columns; b. a random access circuit coupled to the array, the random access circuit comprising a column decoder for concurrently enabling a sense amplifier from each set; c. a first, a second, and a third serial access circuit coupled to the array, the first, the second, and the third serial access circuit respectively comprising a first, a second, and a third plurality of serial access memory cells and a first, a second, and a third pointer decoder for enabling serial access of a serial access memory cell of the respective plurality; and d. a switching circuit comprising a plurality of buses equal in number to the predetermined number, a plurality of first transfer gates for coupling the enabled sense amplifiers to a selected bus of the plurality of buses, and a plurality of second transfer gates for coupling the selected bus to the enabled serial access memory cells.