Method of extracting parameters for circuit simulation

Claim 3

A method according to claim 1, wherein said index symbol data is a data for an index layer having a substantially rectangular area encompassing said bent gate pattern.

Claim 4

A method according to claim 1, wherein said parameters are effective channel widths of said IGFETs.

Claim 5

A method according to claim 3, wherein said bent gate pattern has a serpentine structure having (N f +N r ≧1) bends where N f assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said drain region and N r assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said source region, and said effective channel width W eff is determined as W.sub.eff =ΣW.sub.1 -{N.sub.f (1-K.sub.f)+N.sub.r (1-K.sub.r)}L.sub.eff Where, ΣW l , K f , K r and L eff represent the following: ΣW l : a total length of the bent gate pattern as measured along its central lines, K f , K r : current control capability coefficients of the bends for N f and N r , respectively, and L eff : an effective channel length of the bent gate pattern determined in consideration of unintentional influence of formation of source/drain regions on a channel length.

Claim 6

In a method of circuit simulation for an integrated circuit device having a plurality of field-effect transistors, a parameter extraction method comprising the steps of: (a) preparing layout data representing a layout pattern of one of said plurality of field effect transistors; (b) adding an index symbol data to said layout data when said layout pattern is a non-linear pattern, thereby forming designed pattern data; (c) extracting a circuit parameter of said one of said plurality of field effect transistors based upon the layout data and the designed pattern data; (d) repeating steps (a)-(c) for each of said plurality of field effect transistors; wherein said non-linear pattern is a bent gate pattern having source and drain regions defined on opposite sides thereof; wherein said circuit parameter is an effective channel width of said field effect transistor; and wherein said bent gate pattern has a serpentine structure having (N f +N r ≧1) bends where N f assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said drain region and N r assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said source region, and said effective channel width W eff is determined as W.sub.eff =ΣW.sub.1 -{N.sub.f (1-K.sub.f)+N.sub.r (1-K.sub.r)}L.sub.eff Where, ΣW 1 , K f , K r and L eff represent the following: ΣW 1 : a total length of the bent gate pattern as measured along its central lines, K f , K r : current control capability coefficients of the bends for N f and N r , respectively, and L eff : an effective channel length of the bent gate pattern determined in consideration of unintentional influence of formation of source/drain regions on a channel length.

Claim 7

In a method of circuit simulation for an integrated circuit device having a plurality of field-effect transistors, a parameter extraction method comprising the steps of: (a) preparing layout data representing a layout pattern of one of said plurality of field effect transistors; (b) adding an index symbol data to said layout data when said layout pattern is a non-linear pattern, thereby forming designed pattern data; (c) extracting a circuit parameter of said one of said plurality of field effect transistors based upon the layout data and the designed pattern data; (d) repeating steps (a)-(c) for each of said plurality of field effect transistors; wherein said non-linear pattern is a bent gate pattern having source and drain regions defined on opposite sides thereof; wherein said circuit parameter is an effective channel width of said field effect transistor; and wherein said bent gate pattern has a serpentine structure having (N f +N r ≧1) bends where N f assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said drain region and N r assumes zero or a positive integer and represents a number of times of bending to form an inner angle above said source region, and said effective channel width W eff is determined as W.sub.eff =ΣW.sub.1 -{N.sub.f (1-K.sub.f)+N.sub.r (1-K.sub.r)}L.sub.eff Where, ΣW 1 , K f , K r and L eff represent the following: ΣW 1 : a total length of the bent gate pattern as measured along its central lines, K f , K r : current control capability coefficients of the bends for N f and N r , respectively, and L eff : an effective channel length of the bent gate pattern determined in consideration of unintentional influence of formation of source/drain regions on a channel length.

Claim 8

A method according to claim 5, wherein said index symbol data is data for an index layer having a substantially rectangular area encompassing said bent gate pattern.