Programmable silicon circuit board

Claim 2

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, signal line segments disposed end-to-end and aligned in the same direction on a layer of the substrate, and programmable connection means disposed at predetermined locations of the substrate for selectively connecting at least some of the signal line segments together after the substrate has been manufactured wherein: the programmable connection means includes bridge means interposed between adjacent ends of the signal line segments for selectively connecting at least some of the signal line segments together; and the programmable connection means includes an antifuse material which is capable of being programmed from a high resistance state to an electrically conducting state.

Claim 3

The invention as defined in claim 1, wherein the substrate includes dedicated pad means connected to each of the signal line segments for enabling selected pairs of the signal line segments to be connected together by applying a predetermined electrical pulse across the dedicated pad means of said selected pairs of the signal line segments.

Claim 4

In a wafer-based programmable interconnection substrate for creating a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, first rows of first signal line segments disposed in end-to-end chains in each row on one layer of the substrate and second rows of second signal line segments disposed in end-to-end chains in each row on another layer of the substrate, programmable connection means disposed at predetermined locations of the substrate for selectively connecting at least some of the first signal line segments together, for selectively connecting at least some of the second signal line segments together, and for selectively connecting at least some of the first and second signal line segments together, the signal line connections being capable of being made after the substrate has been manufactured.

Claim 5

In a wafer-based programmable interconnection substrate for creating a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, first rows of first signal line segments disposed in end-to-end chains in each row on one layer of the substrate and second rows of second signal line segments disposed in end-to-end chains in each row on another layer of the substrate, programmable connection means disposed at predetermined locations of the substrate for selectively connecting at least some of the first signal line segments together, for selectively connecting at least some of the second signal line segments together, and for selectively connecting at least some of the first and second signal line segments together, the signal line connections being capable of being made after the substrate has been manufactured.

Claim 6

The invention as defined in claim 3, wherein the programmable connection means includes bridge means interposed between adjacent ends of the first signal line segments and between adjacent ends of the second signal line segments for selectively connecting at least some of the first signal line segments together and for selectively connecting at least some of the second signal line segments together.

Claim 7

The invention as defined in claim 4, wherein the programmable connection means includes an antifuse material which is capable of being programmed from a high resistance state to an electrically conductive state.

Claim 8

The invention as defined in claim 5, wherein the substrate includes dedicated pad means connected to each of the first and second signal line segments for enabling selected pairs of the first signal line segments and selected pairs of the second signal line segments to be connected together by applying a predetermined electrical pulse across the dedicated pad means of the pairs of signal line segments.

Claim 9

The invention as defined in claim 3, wherein the substrate includes a plurality of programmable pad means for enabling an electrical connection to be made between each of the programmable pad means and at least one of a plurality of the first and second signal line segments.

Claim 10

The invention as defined in claim 7, wherein each of the programmable pad means includes first programmable link means extending across a plurality of the first signal line segments for permitting an electrical connection to be made between the programmable pad means and at least one of the first signal line segments, and second programmable link means extending across a plurality of the second signal line segments for permitting an electrical connection to be made between the programmable pad means and at least one of the second signal line segments.

Claim 11

In a wafer-based interconnection substrate for providing a signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, the network having a plurality of signal lines, bonding pads disposed at predetermined locations along the substrate for providing specific electrical connections between integrated circuits and individual signal lines of the substrate, each of the bonding pads having programmable link means for permitting the bonding pads to be selectively connected to at least one of a plurality of the signal lines after the substrate has been manufactured, wherein the programmable link means includes a plurality of link arms extending out from each of the bonding pads to permit the bonding pads to be connected to signal lines disposed on more than one side of the bonding pads.

Claim 12

In a wafer-based interconnection substrate for providing a signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, the network having a plurality of signal lines, bonding pads disposed at predetermined locations along the substrate for providing specific electrical connections between integrated circuits and individual signal lines of the substrate, each of the bonding pads having programmable link means for permitting the bonding pads to be selectively connected to at least one of a plurality of the signal lines after the substrate has been manufactured, wherein the programmable link means includes a plurality of link arms extending out from each of the bonding pads to permit the bonding pads to be connected to signal lines disposed on more than one side of the bonding pads.

Claim 13

The invention as defined in claim 9, wherein the plurality of link arms permits the bonding pads to be connected to signal lines disposed on two different layers of the substrate.

Claim 14

The invention as defined in claim 10, wherein the programmable link means includes four link arms.

Claim 15

The invention as defined in claim 11, wherein the signal lines are disposed in a wavy pattern around each of the bonding pads.

Claim 16

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means including a pad and short outstretched arms and the signal line segments including a plurality of segments crossing each of the arms, each bonding pad means neighboring and unconnected to several line segments, and programmable connection means disposed at the crossings of the segments and the arms for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured.

Claim 17

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means including a pad and short outstretched arms and the signal line segments including a plurality of segments crossing each of the arms, each bonding pad means neighboring and unconnected to several line segments, and programmable connection means disposed at the crossings of the segments and the arms for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured.

Claim 18

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, signal line segments disposed on a layer of the substrate, a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means neighboring several line segments, and programmable connection means disposed at predetermined locations on the substrate for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured, wherein the substrate includes two metallization layers for carrying signals, the bonding pad means includes a pad and integral arm means in each layer, and the signal line segments include a plurality of segments in each layer crossing respective arm means in the other layer, and the programmable connection means are arranged to connect segments and arms.

Claim 19

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, signal line segments disposed on a layer of the substrate, a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means neighboring several line segments, and programmable connection means disposed at predetermined locations on the substrate for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured, wherein the substrate includes two metallization layers for carrying signals, the bonding pad means includes a pad and integral arm means in each layer, and the signal line segments include a plurality of segments in each layer crossing respective arm means in the other layer, and the programmable connection means are arranged to connect segments and arms.

Claim 20

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, signal line segments disposed on a layer of the substrate, a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means neighboring several line segments, and programmable connection means disposed at predetermined locations on the substrate for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured, wherein the substrate includes two metallization layers for carrying signals, the bonding pad means includes a pad and a pair of oppositely outstretched arms in each layer, the signal line segments in each layer include a plurality of segments extending transverse to segments of the other layer and arranged on opposite sides of the pad for selective connection to the respective arms.

Claim 21

In a wafer-based interconnection substrate for providing a programmable signal line network which is capable of interconnecting a plurality of integrated circuits associated with the substrate, signal line segments disposed on a layer of the substrate, a plurality of bonding pad means on the substrate for integrated circuit connection sites, each bonding pad means neighboring several line segments, and programmable connection means disposed at predetermined locations on the substrate for selectively connecting the bonding pad means to any of the several signal line segments after the substrate has been manufactured, wherein the substrate includes two metallization layers for carrying signals, the bonding pad means includes a pad and a pair of oppositely outstretched arms in each layer, the signal line segments in each layer include a plurality of segments extending transverse to segments of the other layer and arranged on opposite sides of the pad for selective connection to the respective arms.

Claim 22

A wafer-based interconnection substrate for providing a programmable network of signal lines capable of interconnecting a plurality of integrated circuits, comprising: electrically conductive wafer means for providing a base which also serves as a power plane for the substrate; first insulator layer means disposed on the wafer means for selectively isolating the wafer means; first electrically conductive layer means disposed on the first insulator layer means for providing an additional power plane; second insulator means disposed on the first electrically conductive layer means for selectively isolating the first electrically conductive layer means; second electrically conductive layer means disposed on the second insulator means for providing a plurality of first signal lines; third insulator means disposed on the second electrically conductive layer means for selectively isolating the first signal lines, the third insulator means also including a plurality of via openings at predetermined locations over the first signal lines; third electrically conductive layer means disposed on the third insulator means for providing a plurality of second signal lines, the second signal lines being oriented relative to the first signal lines such that each of the second signal lines cross over a plurality of the first signal lines, said via openings being disposed at the signal line cross over locations; and antifuse means interposed between the first and second signal lines at predetermined cross over locations for permitting programmable connections to be made between selected ones of the first signal lines and selected ones of the second signal lines; at least one of the second and third electrically conductive layer means also forming bonding pad areas for enabling electrical connections to be made between selected ones of the first and second signal lines and the integrated circuits, the first, second and third insulator means and the first electrically conductive layer means being formed to provide first power connection openings to the wafer means, and the second and third insulator means also being formed to provide second power connection openings to the first electrically conductive layer means.

Claim 23

A wafer-based interconnection substrate for providing a programmable network of signal lines capable of interconnecting a plurality of integrated circuits, comprising: electrically conductive wafer means for providing a base which also serves as a power plane for the substrate; first insulator layer means disposed on the wafer means for selectively isolating the wafer means; first electrically conductive layer means disposed on the first insulator layer means for providing an additional power plane; second insulator means disposed on the first electrically conductive layer means for selectively isolating the first electrically conductive layer means; second electrically conductive layer means disposed on the second insulator means for providing a plurality of first signal lines; third insulator means disposed on the second electrically conductive layer means for selectively isolating the first signal lines, the third insulator means also including a plurality of via openings at predetermined locations over the first signal lines; third electrically conductive layer means disposed on the third insulator means for providing a plurality of second signal lines, the second signal lines being oriented relative to the first signal lines such that each of the second signal lines cross over a plurality of the first signal lines, said via openings being disposed at the signal line cross over locations; and antifuse means interposed between the first and second signal lines at predetermined cross over locations for permitting programmable connections to be made between selected ones of the first signal lines and selected ones of the second signal lines; at least one of the second and third electrically conductive layer means also forming bonding pad areas for enabling electrical connections to be made between selected ones of the first and second signal lines and the integrated circuits, the first, second and third insulator means and the first electrically conductive layer means being formed to provide first power connection openings to the wafer means, and the second and third insulator means also being formed to provide second power connection openings to the first electrically conductive layer means.

Claim 24

A programmable silicon circuit board for interconnecting associated integrated circuits comprising: a silicon substrate supporting a pair of spaced conductive layers and intervening insulator layers, each conductive layer formed into an array of conductors extending in a direction transverse to and crossing the conductors on the other layer; each array of conductors including aligned line segments which in combination extend across the substrate, the aligned line segments having adjacent ends; programmable connection means at each crossing of conductors and at the adjacent ends of the segments for forming selected segments into circuit paths; and bonding pads on the substrate for connection to associated segments.

Claim 25

A programmable silicon circuit board for interconnecting associated integrated circuits comprising: a silicon substrate supporting a pair of spaced conductive layers and intervening insulator layers, each conductive layer formed into an array of conductors extending in a direction transverse to and crossing the conductors on the other layer; each array of conductors including aligned line segments which in combination extend across the substrate, the aligned line segments having adjacent ends; programmable connection means at each crossing of conductors and at the adjacent ends of the segments for forming selected segments into circuit paths; and bonding pads on the substrate for connection to associated segments.

Claim 26

The invention as defined in claim 17 wherein each bonding pad has links extending transversely to a plurality of the line segments; and further programmable connection means at each crossing of the line segments and links for selectively connecting each pad into a circuit path.

Claim 27

The invention as defined in claim 17 wherein the bonding pads each have links respectively crossing line segments on each array of conductors for selective connection between the pads and the line segments.

Claim 28

The invention as defined in claim 17 wherein a programming pad is connected to each segment to provide access for programming connection means.

Claim 29

The invention as defined in claim 20 wherein both the bonding pads and the connections pads are subject to contact by programming apparatus to complete the selective connections, and the bonding pads and the connection pads are each arranged in a pattern defining a cell in the substrate and the pattern is repeated periodically on the substrate to define a plurality of like cells, whereby the bonding pads and the programming pads are arrayed in regular locations to facilitate contact by programming apparatus.

Claim 30

The invention as defined in claim 21 wherein the cells are aligned in the directions of the conductors and each line segment extends across a maximum of three cells.

Claim 31

A programmable silicon circuit board for interconnecting associated integrated circuits comprising: a silicon substrate supporting a pair of spaced conductive layers and intervening insulator layers, each conductive layer being formed into an array of conductors extending in a direction transverse to and crossing the conductors of the other layer; each array of conductors including line segments aligned end-to-end to extend across the substrate, the aligned segments having adjacent ends; a programming pad connected to each line segment; bonding pads on the substrate having links crossing associated segments for selective connection thereto; and programmable connection means at each crossing of conductors and at adjacent ends of segments for forming selected segments into circuit paths after manufacture of the substrate.

Claim 32

A programmable silicon circuit board for interconnecting associated integrated circuits comprising: a silicon substrate supporting a pair of spaced conductive layers and intervening insulator layers, each conductive layer being formed into an array of conductors extending in a direction transverse to and crossing the conductors of the other layer; each array of conductors including line segments aligned end-to-end to extend across the substrate, the aligned segments having adjacent ends; a programming pad connected to each line segment; bonding pads on the substrate having links crossing associated segments for selective connection thereto; and programmable connection means at each crossing of conductors and at adjacent ends of segments for forming selected segments into circuit paths after manufacture of the substrate.